111459 Commits

Author SHA1 Message Date
ea4e4a19b7 PR29653, objcopy/strip: fuzzed small input file induces large output file
_bfd_check_format functions should not print errors or warnings if
they return NULL.  A NULL return means the particular target under
test does not match, so there isn't any reason to make a complaint
about the target.  In fact there isn't a good reason to warn even if
the target matches, except via the _bfd_per_xvec_warn mechanism; Some
other target might be a better match.

This patch tidies pe_bfd_object_p with the above in mind, and
restricts the PE optional header SectionAlignment and FileAlignment
fields somewhat.  I chose to warn on nonsense values rather than
refusing to match.  Refusing to match would be OK too.

	PR 29653
	* peXXigen.c (_bfd_XXi_swap_aouthdr_in): Don't emit error about
	invalid NumberOfRvaAndSizes here.  Limit loop copying data
	directory to IMAGE_NUMBEROF_DIRECTORY_ENTRIES.
	* peicode.h (pe_bfd_object_p): Don't clear and test bfd_error
	around bfd_coff_swap_aouthdr_in.  Warn on invalid SectionAlignment,
	FileAlignment and NumberOfRvaAndSizes.  Don't return NULL on
	invalid NumberOfRvaAndSizes.
2022-10-07 12:30:28 +10:30
fea044ba7b Automatic date update in version.in 2022-10-07 00:00:25 +00:00
0bce60ac7f Fix indentation in riscv-tdep.c
This just fixes some indentation in riscv-tdep.c.
2022-10-06 11:27:11 -06:00
60c90d8c6d gdb/arm: Handle lazy FPU state preservation
Read LSPEN, ASPEN and LSPACT bits from FPCCR and use them together
with FPCAR to identify if lazy FPU state preservation is active for
the current frame.  See "Lazy context save of FP state", in B1.5.7,
also ARM AN298, supported by Cortex-M4F architecture for details on
lazy FPU register stacking.  The same conditions are valid for other
Cortex-M cores with FPU.

This patch has been verified on a STM32F4-Discovery board by:
a) writing a non-zero value (lets use 0x1122334455667788 as an
   example) to all the D-registers in the main function
b) configured the SysTick to fire
c) in the SysTick_Handler, write some other value (lets use
   0x0022446688aaccee as an example) to one of the D-registers (D0 as
   an example) and then do "SVC #0"
d) in the SVC_Handler, write some other value (lets use
   0x0099aabbccddeeff) to one of the D-registers (D0 as an example)

In GDB, suspend the execution in the SVC_Handler function and compare
the value of the D-registers for the SVC_handler frame and the
SysTick_Handler frame.  With the patch, the value of the modified
D-register (D0) should be the new value (0x009..eff) on the
SVC_Handler frame, and the intermediate value (0x002..cee) for the
SysTick_Handler frame.  Now compare the D-register value for the
SysTick_Handler frame and the main frame.  The main frame should
have the initial value (0x112..788).

Signed-off-by: Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
Signed-off-by: Yvan ROUX  <yvan.roux@foss.st.com>
2022-10-06 16:01:10 +02:00
ca10a126c6 [gdb/symtab] Factor out have_complaint
After committing 8ba677d3560 ("[gdb/symtab] Don't complain about function
decls") I noticed that quite a bit of code in read_func_scope is used to decide
whether to issue the "cannot get low and high bounds for subprogram DIE at
$hex" complaint, which executes unnecessarily if we have the default
"set complaints 0".

Fix this by (NFC):
- factoring out new static function have_complaint from macro complaint, and
- using it to wrap the relevant code in read_func_scope.

Tested on x86_64-linux.
2022-10-06 14:53:07 +02:00
80e0c6dc91 gdb: add missing nullptr checks in bpstat_check_breakpoint_conditions
Add a couple of missing nullptr checks in the function
bpstat_check_breakpoint_conditions.

No user visible change after this commit.
2022-10-06 10:01:15 +01:00
d8a77e4c80 gdb: more infrun debug from breakpoint.c
This commit adds additional infrun debug from the breakpoint.c file.
The new debug output all relates to breakpoint condition evaluation.

There is already some infrun debug emitted from the breakpoint.c file,
so hopefully, adding more will not be contentious.  I think the
functions being instrumented make sense as part of the infrun process,
the inferior stops, evaluates the condition, and then either stops or
continues.  This new debug gives more insight into that process.

I had to make the bp_location* argument to find_loc_num_by_location
const, and add a declaration for find_loc_num_by_location.

There should be no user visible changes unless they turn on debug
output.
2022-10-06 10:01:15 +01:00
07443de62b gdb: add some additional debug in mark_async_event_handler
Extend the existing debug printf call to include the previous state of
the async_event_handler object.
2022-10-06 10:01:14 +01:00
a13886e219 RISC-V: Print XTheadMemPair literal as "immediate"
The operand type "Xl(...)" denotes that (...) is a literal.  Specifically,
they are intended to be a constant immediate value.

This commit prints "Xl(...)" operand with dis_style_immediate style,
not dis_style_text.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Use dis_style_immediate on
	the constant literal of the "Xl..." operand.
2022-10-06 02:23:31 +00:00
1554329012 RISC-V: Fix T-Head immediate types on printing
This commit fixes two minor typing-related issues for
T-Head immediate operands.

1.  A signed type must be specified when printing with %i.
2.  unsigned/signed int is not portable enough for max 32-bit immediates.
    Instead, we should use unsigned/signed long.
    The format string is changed accordingly.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Fix T-Head immediate types on
	printing.
2022-10-06 02:23:31 +00:00
f3a8023579 RISC-V: Print comma and tabs as the "text" style
On the RISC-V disassembler, some separators have non-text style when
printed with another word with another style.

This commit splits those, making sure that those comma and tabs are printed
with the "text" style.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Split and print the comma as
	text.  (riscv_disassemble_insn): Split and print tabs as text.
	(riscv_disassemble_data): Likewise.
2022-10-06 02:23:31 +00:00
e0b004c5d5 RISC-V: Optimize riscv_disassemble_data printf
This commit makes types of printf arguments on riscv_disassemble_data
as small as possible (as long as we can preserve the portability) to reduce
the cost of printf (especially on 32-bit host).

opcodes/ChangeLog:

	* riscv-dis.c (riscv_disassemble_data): Use smallest possible type
	to printing data.
2022-10-06 02:23:31 +00:00
2cfc7c876d RISC-V: Fix printf argument types corresponding %x
"%x" format specifier requires unsigned type, not int.  This commit
fixes this issue on the RISC-V disassembler.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Fix printf argument types where
	the format specifier is "%x".
2022-10-06 02:23:31 +00:00
9a76ca16e8 RISC-V: Fix immediates to have "immediate" style
This commit fixes certain print calls on immediate operands to have
dis_style_immediate.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Fix immediates to have
	"immediate" style.  (riscv_disassemble_data): Likewise.
2022-10-06 02:23:31 +00:00
a1509b60cf Automatic date update in version.in 2022-10-06 00:00:17 +00:00
769a27ade5 Re: bfd BLD-POTFILES.in dependencies
Removing $BLD_POTFILES from BFD-POTFILES.in was correct, but left a
hole in dependencies.
make[4]: Entering directory '/home/alan/build/gas/all/bfd/po'
make[4]: *** No rule to make target '../elf32-aarch64.c', needed by '/home/alan/src/binutils-gdb/bfd/po/bfd.pot'.  Stop.

	* Makefile.am (BUILT_SOURCES): Add BUILD_CFILES.
	* Makefile.in: Regenerate.
2022-10-06 09:45:56 +10:30
e87fb6a6d0 x86/gas: support quoted address scale factor in AT&T syntax
An earlier attempt (e68c3d59acd0 ["x86: better respect quotes in
parse_operands()"]) needed undoing (cc0f96357e0b ["x86: permit
parenthesized expressions again as addressing scale factor"]) as far its
effect here went. As indicated back then, the issue is the backwards
scanning of the operand string to find the matching opening parenthesis.
Switch to forward scanning, finding the last outermost unquoted opening
parenthesis (which is the one matching the trailing closing one).
2022-10-05 09:16:24 +02:00
bb5cb85b46 Arm64: support CLEARBHB alias
While the Arm v8 ARM (rev I-a) still doesn't mention this alias, it is
(typically via a macro) already in use in kernels and alike.
2022-10-05 09:15:51 +02:00
306253b2cf PR29647, objdump -S looping
Fuzzed input with this in .debug_line
  [0x0000003b]  Special opcode 115: advance Address by 8 to 0x401180 and Line by -2 to -1

	PR 29647
	* objdump.c (print_line): Don't decrement line number here..
	(dump_lines): ..do so here instead, ensuring loop terminates.
2022-10-05 14:53:41 +10:30
011a136134 Re: stab nearest_line bfd_malloc_and_get_section
It didn't take long for the fuzzers to avoid size checks in
bfd_malloc_and_get_section.  Plug this hole.

	* syms.c (_bfd_stab_section_find_nearest_line): Ignore fuzzed
	sections with no contents.
2022-10-05 14:53:41 +10:30
9c48ba47b3 gprofng: fix build with --enable-pgo-build=lto
gprofng/ChangeLog
2022-10-04  Vladimir Mezentsev  <vladimir.mezentsev@oracle.com>

	PR gprofng/29579
	* libcollector/dispatcher.c: Fix the symbol version in SYMVER_ATTRIBUTE.
	* libcollector/iotrace.c: Likewise.
	* libcollector/linetrace.c: Likewise.
	* libcollector/mmaptrace.c: Likewise.
	* libcollector/synctrace.c: Likewise.
2022-10-04 19:59:49 -07:00
63418f080f Automatic date update in version.in 2022-10-05 00:00:11 +00:00
8f5bc64185 Remove decode_location_spec_default
This removes decode_location_spec_default, inlining it into its sole
caller.

Regression tested on x86-64 Fedora 34.
2022-10-04 16:17:08 -06:00
27e602128b gas: NEWS: Mention the T-Head extensions that were recently added 2022-10-04 13:32:33 -07:00
8ba677d356 [gdb/symtab] Don't complain about function decls
[ Requires "[gdb/symtab] Don't complain about inlined functions" as
submitted here (
https://sourceware.org/pipermail/gdb-patches/2022-September/191762.html ). ]

With the test-case included in this patch, we get:
...
(gdb) ptype main^M
During symbol reading: cannot get low and high bounds for subprogram DIE \
  at 0xc1^M
type = int (void)^M
(gdb) FAIL: gdb.dwarf2/anon-ns-fn.exp: ptype main without complaints
...

The DIE causing the complaint is a function declaration:
...
 <2><c1>: Abbrev Number: 3 (DW_TAG_subprogram)
    <c2>   DW_AT_name        : foo
    <c8>   DW_AT_declaration : 1
...
which is referred to from the DIE representing the function definition:
...
 <1><f4>: Abbrev Number: 7 (DW_TAG_subprogram)
    <f5>   DW_AT_specification: <0xc1>
    <f9>   DW_AT_low_pc      : 0x4004c7
    <101>   DW_AT_high_pc     : 0x7
...
which does contain the low and high bounds.

Fix this by not complaining about function declarations.

Tested on x86_64-linux.
2022-10-04 16:51:03 +02:00
3aeba5cd1c [gdb/symtab] Don't complain about inlined functions
With the test-case included in this patch, we get:
...
(gdb) ptype main^M
During symbol reading: cannot get low and high bounds for subprogram DIE \
  at 0x113^M
During symbol reading: cannot get low and high bounds for subprogram DIE \
  at 0x11f^M
type = int (void)^M
(gdb) FAIL: gdb.dwarf2/inline.exp: ptype main
...

The complaints are about foo, with DW_AT_inline == DW_INL_inlined:
...
 <1><11f>: Abbrev Number: 6 (DW_TAG_subprogram)
    <120>   DW_AT_name        : foo
    <126>   DW_AT_prototyped  : 1
    <126>   DW_AT_type        : <0x10c>
    <12a>   DW_AT_inline      : 1       (inlined)
...
and foo2, with DW_AT_inline == DW_INL_declared_inlined:
...
 <1><113>: Abbrev Number: 5 (DW_TAG_subprogram)
    <114>   DW_AT_name        : foo2
    <11a>   DW_AT_prototyped  : 1
    <11a>   DW_AT_type        : <0x10c>
    <11e>   DW_AT_inline      : 3       (declared as inline and inlined)
...

Fix this by not complaining about inlined functions.

Tested on x86_64-linux.
2022-10-04 16:51:03 +02:00
436a7b5ef2 gdb/riscv: Partial support for instructions up to 176-bit
Because riscv_insn_length started to support instructions up to 176-bit,
we need to increase buf size to 176-bit in size.

Also, that would break an assumption in riscv_insn::decode so this commit
fixes it, noting that instructions longer than 64-bit are not fully
supported yet.
2022-10-04 13:21:41 +00:00
73e30e726c RISC-V: Fix buffer overflow on print_insn_riscv
Because riscv_insn_length started to support instructions up to 176-bit,
we need to increase packet buffer size to 176-bit in size.

include/ChangeLog:

	* opcode/riscv.h (RISCV_MAX_INSN_LEN): Max instruction length for
	use in buffer size.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_riscv): Increase buffer size for max
	176-bit length instructions.
2022-10-04 13:21:41 +00:00
136ea87420 RISC-V: Renamed INSN_CLASS for floating point in integer extensions.
Just added suffix _INX for those INSN_CLASS should be enough to represent
their fpr can be replaced by gpr.
2022-10-04 21:15:51 +08:00
d71eca64e7 Note that at least dejagnu version 1.5.3 is required in order to be ale to run the testsuites.
* README-maintainer-mode: Add a minimum version of dejagnu
	requirement.
2022-10-04 10:54:19 +01:00
e840e61cac opcodes/riscv: style csr names as registers
While reviewing another patch I noticed that RISC-V CSR names are
given the text style, not the register style.  This patch fixes this
mistake.
2022-10-04 09:51:24 +01:00
f4b581f2d1 [AArch64] Update FPSR/FPCR fields for FPU and SVE
I noticed some missing flags/fields from FPSR and FPCR registers in
both the FPU and SVE target descriptions.

This patch adds those and makes the SVE versions of FPSR and FPCR
use the proper flags/bitfields types.
2022-10-04 09:14:34 +01:00
758dd750bc Support objcopy changing compression to or from zstd
Commit 2cac01e3ffff lacked support for objcopy changing compression
style.  Add that support, which meant a rewrite of
bfd_compress_section_contents.  In the process I've fixed some memory
leaks.

	* compress.c (bfd_is_section_compressed_info): Rename from
	bfd_is_section_compressed_with_header and add ch_type param
	to return compression header ch_type field.
	Update all callers.
	(decompress_section_contents): Remove buffer and size params.
	Rewrite.  Update callers.
	(bfd_init_section_compress_status): Free contents on failure.
	(bfd_compress_section): Likewise.
	* elf.c (_bfd_elf_make_section_from_shdr): Support objcopy
	changing between any of the three compression schemes.  Report
	"unable to compress/decompress" rather than "unable to
	initialize compress/decompress status" on compress/decompress
	failures.
	* bfd-in2.h: Regenerate.
2022-10-04 18:42:54 +10:30
034235cebd Re: compress .gnu.debuglto_.debug_* sections if requested
Enable zlib-gnu compression for .gnu.debuglto_.debug_*.  This differs
from zlib-gnu for .debug_* where the name is changed to .zdebug_*.
The name change isn't really needed.

bfd/
	* elf.c (elf_fake_sections): Replace "." with ".z" in debug
	section names only when name was ".d*", ie. ".debug_*".
	(_bfd_elf_assign_file_positions_for_non_load): Likewise.
gas/
	* write.c (compress_debug): Compress .gnu.debuglto_.debug_*
	for zlib-gnu too.  Compress .gnu.linkonce.wi.*.
2022-10-04 18:36:45 +10:30
7afbac7ddd compress .gnu.debuglto_.debug_* sections if requested
Right now, when using LTO, the intermediate object files do contain
debug info in sections starting with .gnu.debuglto_ prefix and are
not compressed when --compress-debug-sections is used.

It's a mistake and we can save quite some disk space. The following
example comes from tramp3d when the corresponding LTO sections
are compressed with zlib:

$ bloaty tramp3d-v4-v2.o -- tramp3d-v4.o
    FILE SIZE        VM SIZE
 --------------  --------------
   +83%     +10  [ = ]       0    [Unmapped]
 -68.0%    -441  [ = ]       0    .gnu.debuglto_.debug_line
 -52.3%    -759  [ = ]       0    .gnu.debuglto_.debug_line_str
 -62.4% -3.24Ki  [ = ]       0    .gnu.debuglto_.debug_abbrev
 -64.8% -1.12Mi  [ = ]       0    .gnu.debuglto_.debug_info
 -88.8% -4.58Mi  [ = ]       0    .gnu.debuglto_.debug_str
 -27.7% -5.70Mi  [ = ]       0    TOTAL

bfd/ChangeLog:

	* elf.c (_bfd_elf_make_section_from_shdr): Compress all debug
	  info sections.

gas/ChangeLog:

	* write.c (compress_debug): Compress also ".gnu.debuglto_.debug_"
	if the compression algorithm is different from zlib-gnu.
2022-10-04 18:36:40 +10:30
bb996692bd RISC-V/gas: allow generating up to 176-bit instructions with .insn
For the time being simply utilize O_big to avoid widening other fields,
bypassing append_insn() etc.
2022-10-04 09:46:11 +02:00
8c07e983a2 RISC-V/gas: don't open-code insn_length()
Use the helper when it can be used.
2022-10-04 09:45:31 +02:00
3b25fc4884 RISC-V/gas: drop stray call to install_insn()
add_fixed_insn(), by calling move_insn(), already invokes install_insn().
2022-10-04 09:45:08 +02:00
f5cb31a8ba RISC-V/gas: drop riscv_subsets static variable
It's fully redundant with the subset_list member of riscv_rps_as.
2022-10-04 09:44:44 +02:00
021205d021 RISC-V: don't cast expressions' X_add_number to long in diagnostics
There's no need for such workarounds anymore now that we use C99
uniformly. This addresses several testsuite failures encountered when
(cross-)building on a 32-bit host.
2022-10-04 09:40:55 +02:00
09fbd1cf93 ignore DWARF debug information for -gsplit-dwarf with dwarf-5
Skip dwo_id for split dwarf.

* dwarf2.c (parse_comp_unit): Skip DWO_id for DW_UT_skeleton.
2022-10-04 09:39:53 +02:00
cf0136a276 Automatic date update in version.in 2022-10-04 00:00:14 +00:00
aef1974a66 Fix self-move warning check for GCC 13+
GCC 13 got the self-move warning (0abb78dda084a14b3d955757c6431fff71c263f3),
but that warning is only checked for clang, resulting in:

/usr/lib/gcc-snapshot/bin/g++ -x c++    -I. -I. -I./config -DLOCALEDIR="\"/tmp/gdb-m68k-linux/share/locale\"" -DHAVE_CONFIG_H -I./../include/opcode -I./../readline/readline/.. -I./../zlib  -I../bfd -I./../bfd -I./../include -I../libdecnumber -I./../libdecnumber  -I./../gnulib/import -I../gnulib/import -I./.. -I.. -I./../libbacktrace/ -I../libbacktrace/  -DTUI=1    -I./.. -pthread  -Wall -Wpointer-arith -Wno-unused -Wunused-value -Wunused-variable -Wunused-function -Wno-switch -Wno-char-subscripts -Wempty-body -Wunused-but-set-parameter -Wunused-but-set-variable -Wno-sign-compare -Wno-error=maybe-uninitialized -Wno-mismatched-tags -Wsuggest-override -Wimplicit-fallthrough=3 -Wduplicated-cond -Wshadow=local -Wdeprecated-copy -Wdeprecated-copy-dtor -Wredundant-move -Wmissing-declarations -Wstrict-null-sentinel -Wformat -Wformat-nonliteral -Werror -g -O2   -c -o unittests/environ-selftests.o -MT unittests/environ-selftests.o -MMD -MP -MF unittests/.deps/environ-selftests.Tpo unittests/environ-selftests.c
unittests/environ-selftests.c: In function 'void selftests::gdb_environ_tests::test_self_move()':
unittests/environ-selftests.c:228:7: error: moving 'env' of type 'gdb_environ' to itself [-Werror=self-move]
  228 |   env = std::move (env);
      |   ~~~~^~~~~~~~~~~~~~~~~
unittests/environ-selftests.c:228:7: note: remove 'std::move' call
cc1plus: all warnings being treated as errors
make[1]: *** [Makefile:1896: unittests/environ-selftests.o] Error 1
make[1]: Leaving directory '/var/lib/laminar/run/gdb-m68k-linux/3/binutils-gdb/gdb'
make: *** [Makefile:13193: all-gdb] Error 2
2022-10-03 16:56:24 +02:00
d1d3123c7b gdb: constify inferior::target_is_pushed
Change-Id: Ia4143b9c63cb76e2c824ba773c66f5c5cd94b2aa
2022-10-03 09:33:01 -04:00
e63ae49b6a [AArch64] Handle W registers as pseudo-registers instead of aliases of X registers
The aarch64 port handles W registers as aliases of X registers. This is
incorrect because X registers are 64-bit and W registers are 32-bit.

This patch teaches GDB how to handle W registers as pseudo-registers of
32-bit, the bottom half of the X registers.

Testcase included.
2022-10-03 14:15:25 +01:00
1ba3a32220 [AArch64] Fix pseudo-register numbering in the presence of unexpected additional registers
When using AArch64 GDB with the QEMU debugging stub (in user mode), we get
additional system registers that GDB doesn't particularly care about, so
it doesn't number those explicitly.

But given the pseudo-register numbers are above the number of real registers,
we need to setup/account for the real registers first before going ahead and
numbering the pseudo-registers.  This has to happen at the end of
aarch64_gdbarch_init, after the call to tdesc_use_registers, as that
updates the total number of real registers.

This is in preparation to supporting pointer authentication for bare metal
aarch64 (QEMU).
2022-10-03 14:15:16 +01:00
907b52f4ce readelf: DO not load section headers from file offset zero
* readelf.c (get_32bit_section_headers): Return false if the
	e_shoff field is zero.
	(get_64bit_section_headers): Likewise.
2022-10-03 13:19:21 +01:00
0129298796 RISC-V: Move supervisor instructions after all unprivileged ones
This location of supervisor instructions is out of place (because many other
privileged instructions are located at the tail but after the supervisor
instructions, we have many unprivileged instructions including bit
manipulation / crypto / vector instructions).

Not only that, this is harmful to implement pseudoinstructions in the latest
'P'-extension proposal (CLROV and RDOV).  This commit moves supervisor
instructions after all unprivileged instructions.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Adjust indents.  Move supervisor
	instructions after all unprivileged instructions.
2022-10-03 11:44:10 +00:00
2820f08f23 Improve GDB's baseclass detection with typedefs
When a class inherits from a typedef'd baseclass, GDB may be unable to
find the baseclass if the user is not using the typedef'd name, as is
tested on gdb.cp/virtbase2.exp; the reason that test case is working
under gcc is that the dwarf generated by gcc links the class to the
original definition of the baseclass, not to the typedef.  If the
inheritance is linked to the typedef, such as how clang does it,
gdb.cp/virtbase2.exp starts failing.

This can also be seen in gdb.cp/impl-this.exp, when attempting to print
D::Bint::i, and GDB not being able to find the baseclass Bint.

This happens because searching for baseclasses only uses the macro
TYPE_BASECLASS_NAME, which returns the typedef'd name. However, we can't
switch that macro to checking for typedefs, otherwise we wouldn't be
able to find the typedef'd name anymore. This is fixed by searching for
members or baseclasses by name, we check both the saved name and the
name after checking for typedefs.

This also fixes said long-standing bug in gdb.cp/impl-this.exp when the
compiler adds information about typedefs in the debuginfo.
2022-10-03 10:09:30 +02:00
7b4f240762 RISC-V: Assign DWARF numbers to vector registers
This commit assigns DWARF register numbers to vector registers (v0-v31:
96..127) to implement RISC-V DWARF Specification version 1.0-rc4
(now in the frozen state):

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4

binutils/ChangeLog:

	* dwarf.c (dwarf_regnames_riscv): Assign DWARF register numbers
	96..127 to vector registers v0-v31.

gas/ChangeLog:

	* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Support
	vector registers.
	* testsuite/gas/riscv/dw-regnums.s: Add vector registers to the
	DWARF register number test.
	* testsuite/gas/riscv/dw-regnums.d: Likewise.
2022-10-03 04:04:35 +00:00