910 Commits

Author SHA1 Message Date
e74eb924c2 * m32r.opc (parse_slo16): Fix bad application of previous patch. 2005-10-19 14:44:17 +00:00
471e4e36fc * bfin-dis.c (print_insn_bfin): Do proper endian transform when
reading instruction from memory.
2005-10-18 16:39:41 +00:00
5e03663f3d m32r.opc (parse_slo16): Better version of previous patch. 2005-10-18 07:53:17 +00:00
ab7c9a26e5 m32r.opc (parse_slo16): Do not assume a 32-bit host word size. 2005-10-14 08:33:27 +00:00
19590ef7f6 2005-10-08 James Lemke <jim@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): Fix mask for various Maverick CDP
	operations.
2005-10-08 14:52:07 +00:00
6edfbbad08 bfd/
* elf32-arm.c (elf32_arm_check_relocs): Avoid aliasing warnings from
	GCC.
	(elf32_arm_size_dynamic_sections): Likewise.
	* ecofflink.c (bfd_ecoff_debug_one_external): Likewise.
	* elf32-hppa.c (elf32_hppa_check_relocs): Likewise.
	* elf32-m32r.c (m32r_elf_check_relocs): Likewise.
	* elf32-m68k.c (elf_m68k_check_relocs): Likewise.
	* elf32-ppc.c (ppc_elf_check_relocs): Likewise.
	* elf32-s390.c (elf_s390_check_relocs): Likewise.
	(elf_s390_size_dynamic_sections): Likewise.
	* elf32-sh.c (sh_elf_check_relocs): Likewise.
	* elf64-ppc.c (ppc64_elf_check_relocs, dec_dynrel_count)
	(ppc64_elf_size_dynamic_sections): Likewise.
	* elf64-s390.c (elf_s390_check_relocs): Likewise.
	(elf_s390_size_dynamic_sections): Likewise.
	* elfxx-mips.c (_bfd_mips_elf_finish_dynamic_sections): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise.
	(_bfd_sparc_elf_size_dynamic_sections): Likewise.
	* ieee.c (ieee_slurp_section_data): Likewise.
	* oasys.c (oasys_slurp_section_data): Likewise.
opcodes/
	* ppc-dis.c (struct dis_private): Remove.
	(powerpc_dialect): Avoid aliasing warnings.
	(print_insn_big_powerpc, print_insn_little_powerpc): Likewise.
2005-10-06 19:21:14 +00:00
095f284399 oops - delayed commit for addtion of Irish translation for gprof and opcodes 2005-10-03 10:52:38 +00:00
fdd3b9b33b 2005-09-30 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerated.
	* aclocal.m4: Likewise.
	* configure: Likewise.
2005-09-30 18:05:59 +00:00
4b7f6baa0b * Makefile.am: Bfin support.
* Makefile.in: Regenerated.
	* aclocal.m4: Regenerated.
	* bfin-dis.c: New file.
	* configure.in: Bfin support.
	* configure: Regenerated.
	* disassemble.c (ARCH_bfin): Define.
	(disassembler): Add case for bfd_arch_bfin.
2005-09-30 15:28:52 +00:00
1a114b1284 gas/testsuite/
2005-09-28  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/x86-64-stack.s, gas/i386/x86-64-stack.d,
	gas/i386/x86-64-stack-suffix.d, gas/i386/x86-64-stack-intel.d: New.
	* gas/i386/i386.exp: Run new tests.

ld/testsuite/
2005-09-28  Jan Beulich  <jbeulich@novell.com>

	* ld-x86-64/tlspic.dd: Adjust.

opcodes/
2005-09-28  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (stack_v_mode): Renamed from branch_v_mode.
	(indirEv): Use it.
	(stackEv): New.
	(Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions.
	(dis386): Document and use new 'V' meta character. Use it for
	single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop
	opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov.
	(putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark
	data prefix as used whenever DFLAG was examined. Handle 'V'.
	(intel_operand_size): Use stack_v_mode.
	(OP_E): Use stack_v_mode, but handle only the special case of
	64-bit mode without operand size override here; fall through to
	v_mode case otherwise.
	(OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode
	and no operand size override is present.
	(OP_J): Use get32s for obtaining the displacement also when rex64
	is present.
2005-09-28 15:34:53 +00:00
3eb17e6bd2 2005-09-08 Paul Brook <paul@codesourcery.com>
bfd/
	* reloc.c: Rename BFD_RELOC_ARM_SMI to BFD_RELOC_ARM_SMC.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
opcodes/
	* arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.
gas/
	* config/tc-arm.c (do_smi, do_t_smi): Rename ...
	(do_smc, do_t_smc): ... to this.
	(insns): Remane smi to smc.
	(md_apply_fix, tc_gen_reloc): Rename BFD_RELOC_ARM_SMI to
	BFD_RELOC_ARM_SMC.
gas/testsuite/
	* gas/arm/arch6zk.d: Rename smi to smc.
	* gas/arm/arch6zk.s: Ditto.
	* gas/arm/thumb32.d: Ditto.
	* gas/arm/thumb32.s: Ditto.
2005-09-08 12:49:27 +00:00
61cc026711 * mips-opc.c (MT32): New define.
(mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
bottom to avoid opcode collision with "mftr" and "mttr".
Add MT instructions.
* mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
(print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
formats.
2005-09-06 18:46:57 +00:00
b13dd07a55 2005-09-02 Paul Brook <paul@codesourcery.com>
* arm-dis.c (coprocessor_opcodes): Add null terminator.
2005-09-02 14:54:27 +00:00
8f06b2d82f 2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/
	* libbdf.h: Regenerate.
	* bfd-in2.h: Regenerate.
	* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
	BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
	* config/tc-arm.c (encode_arm_cp_address): Use
	BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
	(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
	mode.
	(md_assemble): Only allow coprocessor instructions when Thumb-2 is
	available.
	(cCE, cC3): Define.
	(insns): Use them for coprocessor instructions.
	(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
	(get_thumb32_insn): New function.
	(put_thumb32_insn): New function.
	(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
	BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
	* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
	gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
	gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
	* arm-dis.c (coprocessor_opcodes): New.
	(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
	(print_insn_coprocessor): New function.
	(print_insn_arm): Use print_insn_coprocessor.  Remove coprocessor
	format characters.
	(print_insn_thumb32): Use print_insn_coprocessor.
2005-09-02 13:12:45 +00:00
a2dfd01fa7 2005-08-30 Paul Brook <paul@codesourcery.com>
opcodes/
	* arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
gas/testsuite/
	* gas/arm/thumb.d: Change "sub rn, rn, rn" to "subs rn, rn, rn".
	* gas/arm/thumb32.d: Ditto.
2005-08-30 11:21:59 +00:00
3f31e633c2 opcodes/
2005-08-26  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (intel_operand_size): New, broken out from OP_E for
	re-use.
	(OP_E): Call intel_operand_size, move call site out of mode
	dependent code.
	(OP_OFF): Call intel_operand_size if suffix_always. Remove
	ATTRIBUTE_UNUSED from parameters.
	(OP_OFF64): Likewise.
	(OP_ESreg): Call intel_operand_size.
	(OP_DSreg): Likewise.
	(OP_DIR): Use colon rather than semicolon as separator of far
	jump/call operands.

gas/testsuite/
2005-08-26  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/intelok.d: Adjust.
2005-08-26 15:33:43 +00:00
fd25c5a9db * mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.
(mips_builtin_opcodes): Add DSP instructions.
* mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
mips64, mips64r2.
(print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
operand formats.
2005-08-25 18:12:44 +00:00
dd8b7c222e * mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
instructions to the table.
2005-08-23 11:06:10 +00:00
848cf006a0 Remove a29k files. 2005-08-18 03:59:24 +00:00
c17ae8a24e Remove a29k support. 2005-08-18 03:51:51 +00:00
36ae0db314 gas/
* config/tc-ppc.c (parse_cpu): Add -me300 support.
	(md_show_usage): Likewise.
	* doc/c-ppc.texi (PowerPC-Opts): Document it.
include/opcode/
	* ppc.h (PPC_OPCODE_E300): Define.
opcodes/
	* ppc-dis.c (powerpc_dialect): Handle e300.
	(print_ppc_disassembler_options): Likewise.
	* ppc-opc.c (PPCE300): Define.
	(powerpc_opcodes): Mark icbt as available for the e300.
binutils/
	* doc/binutils.texi (objdump): Document -M e300.
2005-08-15 15:37:15 +00:00
63a3357b7b * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.
Use "rp" instead of "%r2" in "b,l" insns.
2005-08-14 01:15:34 +00:00
ad101263eb * s390-dis.c (print_insn_s390): Print unsigned operands with %u.
* s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
	(main): Likewise.
	* s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
	and 4 bit optional masks.
	(INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
	INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
	(MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
	MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
	(s390_opformats): Likewise.
	* s390-opc.txt: Add new instructions for cpu type z9-109.
2005-08-12 18:03:03 +00:00
f1fa109355 * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%". 2005-08-05 17:52:06 +00:00
e9f89963c4 2005-07-29 Paul Brook <paul@codesourcery.com>
bfd/
	* reloc.c: Add BFD_RELOC_ARM_T32_ADD_PC12.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
gas/
	* config/tc-arm.c (T16_32_TAB): Add "addr". Fix encoding of push and
	pop.
	(do_t_addr): Implement 32-bit variant.
	(do_t_push_pop): Make some errors warnings.  Handle single register
	32-bit case.
	(insns): Use tCE for adr.
	(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_ADD_PC12.
	(md_apply_fix): Ditto.
gas/testsuite/
	* gas/arm/thumb32.d: Fix expected output for writeback addressing
	modes.  Add single high reg push/pop test.
	* gas/asm/thumb32.s: Add single high reg push/pop test.
opcodes/
	* arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
2005-07-29 17:39:39 +00:00
92e90b6eb3 2005-07-29 Paul Brook <paul@codesourcery.com>
bfd/
	* reloc.c (BFD_RELOC_ARM_T32_IMM12): Add.
	* bfd-in2.h: Regeenrate.
	* libbfd.h: Regenerate.
gas/
	* config/tc-arm.c (parse_tb): New function.
	(enum operand_parse_code): Add OP_TB.
	(parse_operands): Handle OP_TB.
	(do_t_add_sub_w, do_t_tb): New functions.
	(insns): Add entries for addw, subw, tbb and tbh.
	(md_apply_fix): Handle BFD_RELOC_ARM_T32_IMM12.
gas/testsuite/
	* gas/arm/thumb32.s: Add tests for addw, subw, tbb and tbh.
	* gas/arm/thumb32.d: Ditto.
opcodes/
	* arm-dis.c (thumb32_opc): Fix addressing mode for tbh.
	(print_insn_thumb32): Fix decoding of thumb2 'I' operands.
2005-07-29 17:28:33 +00:00
c5f5f1f476 missed from 2005-07-18 commit 2005-07-26 11:08:59 +00:00
fd54057a29 [bfd]
* reloc.c: Remove unused M32C relocs, add BFD_RELOC_M32C_HI8.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.

	* elf32-m32c.c (m32c_elf_howto_table): Add R_M32C_8, R_M32C_LO16,
	R_M32C_HI8, R_M32C_HI16.
	(m32c_reloc_map): Likewise.
	(m32c_elf_relocate_section): Add R_M32C_HI8 and R_M32C_HI16.

[cpu]
	* m32c.opc (parse_unsigned8): Add %dsp8().
	(parse_signed8): Add %hi8().
	(parse_unsigned16): Add %dsp16().
	(parse_signed16): Add %lo16() and %hi16().
	(parse_lab_5_3): Make valuep a bfd_vma *.

[gas]
	* config/tc-m32c.c (md_cgen_lookup_reloc): Add 8 bit operands.
	Support %mod() modifiers from opcodes.
	* doc/c-m32c.texi (M32C-Modifiers): New section.

[include/elf]

	* m32c.h: Add R_M32C_8, R_M32C_LO16, R_M32C_HI8, and R_M32C_HI16.

[opcodes]
	* m32c-asm.c Regenerate.
	* m32c-dis.c Regenerate.
2005-07-26 03:21:53 +00:00
760c0f6a1a * disassemble.c (disassemble_init_for_target): M32C ISAs are
enums, so convert them to bit masks, which attributes are.
2005-07-20 19:36:54 +00:00
85da3a565d Add ChangeLog entries for yesterdays deltas (oops!) 2005-07-19 10:01:32 +00:00
22cbf2e74a gas/testsuite/
2005-07-18  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add suffix.

	* gas/i386/suffix.d: New file.
	* gas/i386/suffix.s: Likewise.

opcodes/

2005-07-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PNI_Fixup): Update comment.
	(VMX_Fixup): Properly handle the suffix check.
2005-07-19 04:11:19 +00:00
e729279b04 Fix building for MS1 and M32C.
Restore alpha- sorting to the architecture tables.
2005-07-18 14:13:36 +00:00
0aea0460fe * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode
mfctl disassembly.
2005-07-17 02:26:26 +00:00
0f82ff91a0 bfd/
* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
opcodes/
	* Makefile.am: Run "make dep-am".
	(stamp-m32c): Fix cpu dependencies.
	* Makefile.in: Regenerate.
	* ip2k-dis.c: Regenerate.
binutils/
	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
gas/
	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
ld/
	* Makefile.am: Run "make dep-am".
	(emipsidt.c, emipsidtl.c): Depend on generic.em.
	* Makefile.in: Regenerate.
2005-07-16 02:03:55 +00:00
90700ea20f gas/
2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* gas/config/tc-i386.h (CpuVMX): New.
	(CpuUnknownFlags): Add CpuVMX.

gas/testsuite/

2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add vmx and x86-64-vmx.

	* gas/i386/vmx.d: New file.
	* gas/i386/vmx.s: Likewise.
	* gas/i386/x86-64-vmx.d: Likewise.
	* gas/i386/x86-64-vmx.s: Likewise.

include/opcode/

2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel VMX Instructions.

opcodes/

2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
	(VMX_Fixup): New. Fix up Intel VMX Instructions.
	(Em): New.
	(Gm): New.
	(VM): New.
	(dis386_twobyte): Updated entries 0x78 and 0x79.
	(twobyte_has_modrm): Likewise.
	(grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
	(OP_G): Handle m_mode.
2005-07-15 13:49:53 +00:00
49f58d10f8 ChangeLog:
2005-07-14  Jim Blandy  <jimb@redhat.com>

	* configure.in: Add cases for Renesas m32c.
	* configure: Regenerated.

bfd/ChangeLog:
2005-07-14  Jim Blandy  <jimb@redhat.com>

	Add support for m32c-*-elf (Renesas m32c and m16c).
	* Makefile.am (ALL_MACHINES): Add cpu-m32c.lo.
	(ALL_MACHINES_CFILES): Add cpu-m32c.c.
	(BFD32_BACKENDS): Add elf32-m32c.lo.
	(BFD32_BACKENDS_CFILES): Add elf32-m32c.c.
	(cpu-m32c.lo, elf32-m32c.lo): New rules, generated by 'make dep-am'.
	* Makefile.in: Regenerated.
	* archures.c (bfd_arch_m32c, bfd_mach_m16c, bfd_mach_m32c): New
	arch and mach codes.
	(bfd_m32c_arch): New arch info object.
	(bfd_archures_list): List bfd_m32c_arch.
	* bfd-in2.h: Regenerated.
	* config.bfd: Add case for the m32c.
	* configure.in: Add case for the m32c.
	* configure: Regenerated.
	* cpu-m32c.c, elf32-m32c.c: New files.
	* libbfd.h: Regenerated.
	* targets.c (bfd_elf32_m32c_vec): Declare.
	(_bfd_target_vector): List bfd_elf32_m32c_vec.

binutils/ChangeLog:
2005-07-14  Jim Blandy  <jimb@redhat.com>

	* readelf.c: #include "elf/m32c.h"
	(guess_is_rela, dump_relocations, get_machine_name): Add cases for
	EM_M32C.
	* Makefile.am (readelf.o): Update dependencies.
	* Makefile.in: Regenerated.

cpu/ChangeLog:
2005-07-14  Jim Blandy  <jimb@redhat.com>

	* m32c.cpu, m32c.opc: Machine description for the Renesas M32C.

gas/ChangeLog:
2005-07-14  Jim Blandy  <jimb@redhat.com>

	Add support for the Renesas M32C.
	* Makefile.am (CPU_TYPES): List m32c.
	(TARGET_CPU_CFILES): List config/tc-m32c.c.
	(TARGET_CPU_HFILES): List config/tc-m32c.h.
	* configure.in: Add case for m32c.
	* configure.tgt: Add cases for m32c and m32c-*-elf.
	* configure: Regenerated.
	* config/tc-m32c.c, config/tc-m32c.h: New files.
	* doc/Makefile.am (CPU_DOCS): Add c-m32c.texi.
	* doc/Makefile.in: Regenerated.
	* doc/all.texi: Set M32C.
	* doc/as.texinfo: Add text for the M32C-specific options and line
	comment characters, and refer to c-m32c.texi.
	* doc/c-m32c.texi: New file.

include/ChangeLog:
2005-07-14  Jim Blandy  <jimb@redhat.com>

	* dis-asm.h (print_insn_m32c): New declaration.

include/elf/ChangeLog:
2005-07-14  Jim Blandy  <jimb@redhat.com>

	Add support for Renesas M32C and M16C.
	* common.h (EM_M32C): New machine number.
	* m32c.h: New file.

ld/ChangeLog:
2005-07-14  Jim Blandy  <jimb@redhat.com>

	Add support for the Renesas M32C and M16C.
	* Makefile.am (ALL_EMULATIONS): Add eelf32m32c.o.
	(eelf32m32c.c): New target.
	* Makefile.in: Regenerated.
	* configure.tgt: Add case for m32c-*-elf.
	* emulparams/elf32m32c.sh: New file.

opcodes/ChangeLog:
2005-07-14  Jim Blandy  <jimb@redhat.com>

	Add support for the Renesas M32C and M16C.
	* m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
	* m32c-desc.h, m32c-opc.h: New.
	* Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
	(CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
	m32c-opc.c.
	(ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
	m32c-ibld.lo, m32c-opc.lo.
	(CLEANFILES): List stamp-m32c.
	(M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
	(CGEN_CPUS): Add m32c.
	(m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
	(m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
	(m32c_opc_h): New variable.
	(stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
	(m32c-opc.lo): New rules.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_m32c_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_m32c): New.
	[ARCH_m32c]: #include "m32c-desc.h".
	(disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
	(disassemble_init_for_target) [ARCH_m32c]: Same.

	* cgen-ops.h, cgen-types.h: New files.
	* Makefile.am (HFILES): List them.
	* Makefile.in: Regenerated.
2005-07-14 22:52:28 +00:00
0fd3a4776c Kaveh Ghazi's printf format attribute checking patch.
bfd:
	* elf32-xtensa.c (vsprint_msg): Add format attribute.  Fix
	format bugs.
	* vms.h (_bfd_vms_debug): Add format attribute.
	(_bfd_vms_debug, _bfd_hexdump): Fix typos.

binutils:
	* bucomm.h (report): Add format attribute.
	* dlltool.c (inform): Likewise.
	* dllwrap.c (display, inform, warn): Likewise.
	* objdump.c (objdump_sprintf): Likewise.
	* readelf.c (error, warn): Likewise.  Fix format bugs.

gas:
	* config/tc-tic30.c (debug): Add format attribute.  Fix format
	bugs.

include:
	* dis-asm.h (fprintf_ftype): Add format attribute.

opcodes:
	* arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
	d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
	ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
	m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
	ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
	v850-dis.c: Fix format bugs.
	* ia64-gen.c (fail, warn): Add format attribute.
	* or32-opc.c (debug): Likewise.
2005-07-07 19:27:52 +00:00
22f8fcbd5c arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction disassembly
pattern.
vfp1xD.d: Adjust expected fadds disassemblies now that the dissassembler has
  been fixed.
2005-07-07 11:37:10 +00:00
d125c27b97 * Makefile.am (stamp-m32r): Fix path to cpu files.
(stamp-m32r, stamp-iq2000): Likewise.
	* Makefile.in: Regenerate.
	* m32r-asm.c: Regenerate.
	* po/POTFILES.in: Remove arm-opc.h.  Add ms1-asm.c, ms1-desc.c,
	ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
2005-07-06 08:19:39 +00:00
3ec2b351bd Fix compile time warnings from a GCC 4.0 compiler 2005-07-05 15:07:46 +00:00
3012383869 gas/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* config/tc-i386.h (CpuSVME): New.
	(CpuUnknownFlags): Include CpuSVME.
	* config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron
	as alias of sledgehammer.
	(md_assemble): Include invlpga in the check for insns with two source
	operands.
	(process_operands): Include SVME insns in the check for ignored
	segment overrides. Adjust diagnostic.
	(i386_index_check): Special-case SVME insns with memory operands.

gas/testsuite/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/svme.d: New.
	* gas/i386/svme.s: New.
	* gas/i386/svme64.d: New.
	* gas/i386/i386.exp: Run new tests.

include/opcode/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add new insns.

opcodes/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (SVME_Fixup): New.
	(grps): Use it for the lidt entry.
	(PNI_Fixup): Call OP_M rather than OP_E.
	(INVLPG_Fixup): Likewise.
2005-07-05 07:16:54 +00:00
b0eec63e04 2005-07-04 H.J. Lu <hongjiu.lu@intel.com>
* tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
2005-07-04 17:51:36 +00:00
47b0e7ad8c Update function declarations to ISO C90 formatting 2005-07-01 11:16:33 +00:00
cc16ba8c4f * m68k-dis.c: Use ISC C90.
* m68k-opc.c: Formatting fixes.
2005-06-23 11:18:26 +00:00
4b185e973e * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
instructions to the table; seb/seh/sew/zeb/zeh/zew.
2005-06-16 17:01:12 +00:00
ac18822241 2005-06-15 Dave Brolley <brolley@redhat.com>
Contribute Morpho ms1 on behalf of Red Hat
        * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
        ms1-opc.h: New files, Morpho ms1 target.

        2004-05-14  Stan Cox  <scox@redhat.com>

        * disassemble.c (ARCH_ms1): Define.
        (disassembler): Handle bfd_arch_ms1

        2004-05-13  Michael Snyder  <msnyder@redhat.com>

        * Makefile.am, Makefile.in: Add ms1 target.
        * configure.in: Ditto.
2005-06-15 16:23:54 +00:00
6b5d3a4d35 opcodes:
* arm-opc.h: Delete; fold contents into ...
	* arm-dis.c: ... here.  Move includes of internal COFF headers
	next to includes of internal ELF headers.
	(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
	(struct arm_opcode): Rename struct opcode32.  Make 'assembler' const.
	(struct thumb_opcode): Rename struct opcode16.  Make 'assembler' const.
	(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
	(iwmmxt_wwnames, iwmmxt_wwssnames):
	Make const.
	(regnames): Remove iWMMXt coprocessor register sets.
	(iwmmxt_regnames, iwmmxt_cregnames): New statics.
	(get_arm_regnames): Adjust fourth argument to match above changes.
	(set_iwmmxt_regnames): Delete.
	(print_insn_arm): Constify 'c'.  Use ISO syntax for function
	pointer calls.  Expand sole use of BDISP.  Use iwmmxt_regnames
	and iwmmxt_cregnames, not set_iwmmxt_regnames.
	(print_insn_thumb16, print_insn_thumb32): Constify 'c'.  Use
	ISO syntax for function pointer calls.
include:
	* dis-asm.h (get_arm_regnames): Update prototype.
2005-06-08 17:27:41 +00:00
4a5329c63a * arm-dis.c: Split up the comments describing the format codes, so
that the ARM and 16-bit Thumb opcode tables each have comments
	preceding them that describe all the codes, and only the codes,
	valid in those tables.  (32-bit Thumb table is already like this.)
	Reorder the lists in all three comments to match the order in
	which the codes are implemented.
	Remove all forward declarations of static functions.  Convert all
	function definitions to ISO C format.
	(print_insn_arm, print_insn_thumb16, print_insn_thumb32):
	Return nothing.
	(print_insn_thumb16): Remove unused case 'I'.
	(print_insn): Update for changed calling convention of subroutines.
2005-06-07 22:16:52 +00:00
3d456fa193 gas/testsuite/
2005-05-25  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/intelok.d: Account for 32-bit displacements being shown
	in hex.

opcodes/
2005-05-25  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
	hex (but retain it being displayed as signed). Remove redundant
	checks. Add handling of displacements for 16-bit addressing in Intel
	mode.
2005-05-25 06:50:23 +00:00
2888cb7a54 opcodes/
2005-05-25  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (prefix_name): Remove pointless mode_64bit check.
	(OP_E): Remove redundant REX_EXTZ handling. Remove pointless
	masking of 'rm' in 16-bit memory address handling.
2005-05-25 06:47:58 +00:00