mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-10-13 10:55:46 +08:00
2005-09-02 Paul Brook <paul@codesourcery.com>
bfd/ * libbdf.h: Regenerate. * bfd-in2.h: Regenerate. * reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. gas/ * config/tc-arm.c (encode_arm_cp_address): Use BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode. (do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb mode. (md_assemble): Only allow coprocessor instructions when Thumb-2 is available. (cCE, cC3): Define. (insns): Use them for coprocessor instructions. (md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM. (get_thumb32_insn): New function. (put_thumb32_insn): New function. (md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. gas/testsuite/ * gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s, gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d, gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files. opcodes/ * arm-dis.c (coprocessor_opcodes): New. (arm_opcodes, thumb32_opcodes): Remove coprocessor insns. (print_insn_coprocessor): New function. (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor format characters. (print_insn_thumb32): Use print_insn_coprocessor.
This commit is contained in:
Paul Brook
@ -1,3 +1,10 @@
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2005-09-02 Paul Brook <paul@codesourcery.com>
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* libbdf.h: Regenerate.
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* bfd-in2.h: Regenerate.
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* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
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BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
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2005-09-01 Dmitry Diky <diwil@spec.ru>
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* elf32-msp430.c (msp430_elf_relax_delete_bytes): Do not adjust
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@ -2881,6 +2881,8 @@ pc-relative or some form of GOT-indirect relocation. */
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BFD_RELOC_ARM_MULTI,
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BFD_RELOC_ARM_CP_OFF_IMM,
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BFD_RELOC_ARM_CP_OFF_IMM_S2,
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BFD_RELOC_ARM_T32_CP_OFF_IMM,
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BFD_RELOC_ARM_T32_CP_OFF_IMM_S2,
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BFD_RELOC_ARM_ADR_IMM,
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BFD_RELOC_ARM_LDR_IMM,
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BFD_RELOC_ARM_LITERAL,
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@ -1219,6 +1219,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
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"BFD_RELOC_ARM_MULTI",
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"BFD_RELOC_ARM_CP_OFF_IMM",
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"BFD_RELOC_ARM_CP_OFF_IMM_S2",
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"BFD_RELOC_ARM_T32_CP_OFF_IMM",
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"BFD_RELOC_ARM_T32_CP_OFF_IMM_S2",
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"BFD_RELOC_ARM_ADR_IMM",
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"BFD_RELOC_ARM_LDR_IMM",
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"BFD_RELOC_ARM_LITERAL",
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@ -2753,6 +2753,10 @@ ENUMX
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BFD_RELOC_ARM_CP_OFF_IMM
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ENUMX
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BFD_RELOC_ARM_CP_OFF_IMM_S2
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ENUMX
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BFD_RELOC_ARM_T32_CP_OFF_IMM
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ENUMX
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BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
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ENUMX
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BFD_RELOC_ARM_ADR_IMM
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ENUMX
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@ -1,3 +1,19 @@
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2005-09-02 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (encode_arm_cp_address): Use
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BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
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(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
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mode.
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(md_assemble): Only allow coprocessor instructions when Thumb-2 is
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available.
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(cCE, cC3): Define.
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(insns): Use them for coprocessor instructions.
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(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
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(get_thumb32_insn): New function.
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(put_thumb32_insn): New function.
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(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
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BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
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2005-09-02 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (opcode_lookup): Look for infix opcode when
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1518
gas/config/tc-arm.c
1518
gas/config/tc-arm.c
File diff suppressed because it is too large
Load Diff
@ -1,3 +1,9 @@
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2005-09-02 Paul Brook <paul@codesourcery.com>
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* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
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gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
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gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
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2005-09-02 Paul Brook <paul@codesourcery.com>
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* gas/arm/fpa-mem.d: Test "stfpls".
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3
gas/testsuite/gas/arm/vfp-bad_t2.d
Normal file
3
gas/testsuite/gas/arm/vfp-bad_t2.d
Normal file
@ -0,0 +1,3 @@
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#name: Thumb-2 VFP errors
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#as: -mfpu=vfp
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#error-output: vfp-bad_t2.l
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9
gas/testsuite/gas/arm/vfp-bad_t2.l
Normal file
9
gas/testsuite/gas/arm/vfp-bad_t2.l
Normal file
@ -0,0 +1,9 @@
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[^:]*: Assembler messages:
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[^:]*:7: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8'
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[^:]*:8: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!'
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[^:]*:9: Error: instruction does not support writeback -- `fsts s0,\[r0\],#8'
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[^:]*:10: Error: instruction does not support writeback -- `fsts s0,\[r0,#-8\]!'
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[^:]*:11: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8'
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[^:]*:12: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!'
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[^:]*:13: Error: instruction does not support writeback -- `flds s0,\[r0\],#8'
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[^:]*:14: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!'
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14
gas/testsuite/gas/arm/vfp-bad_t2.s
Normal file
14
gas/testsuite/gas/arm/vfp-bad_t2.s
Normal file
@ -0,0 +1,14 @@
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.global entry
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@ Same as vfp-bad.s, but for Thumb-2
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.syntax unified
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.thumb
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.text
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entry:
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fstd d0, [r0], #8
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fstd d0, [r0, #-8]!
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fsts s0, [r0], #8
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fsts s0, [r0, #-8]!
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fldd d0, [r0], #8
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fldd d0, [r0, #-8]!
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flds s0, [r0], #8
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flds s0, [r0, #-8]!
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205
gas/testsuite/gas/arm/vfp1_t2.d
Normal file
205
gas/testsuite/gas/arm/vfp1_t2.d
Normal file
@ -0,0 +1,205 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: Thumb-2 VFP Double-precision instructions
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#as: -mfpu=vfp
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# Test the ARM VFP Double Precision instructions
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+000 <[^>]*> eeb4 0bc0 fcmped d0, d0
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0+004 <[^>]*> eeb5 0bc0 fcmpezd d0
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0+008 <[^>]*> eeb4 0b40 fcmpd d0, d0
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0+00c <[^>]*> eeb5 0b40 fcmpzd d0
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0+010 <[^>]*> eeb0 0bc0 fabsd d0, d0
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0+014 <[^>]*> eeb0 0b40 fcpyd d0, d0
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0+018 <[^>]*> eeb1 0b40 fnegd d0, d0
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0+01c <[^>]*> eeb1 0bc0 fsqrtd d0, d0
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0+020 <[^>]*> ee30 0b00 faddd d0, d0, d0
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0+024 <[^>]*> ee80 0b00 fdivd d0, d0, d0
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0+028 <[^>]*> ee00 0b00 fmacd d0, d0, d0
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0+02c <[^>]*> ee10 0b00 fmscd d0, d0, d0
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0+030 <[^>]*> ee20 0b00 fmuld d0, d0, d0
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0+034 <[^>]*> ee00 0b40 fnmacd d0, d0, d0
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0+038 <[^>]*> ee10 0b40 fnmscd d0, d0, d0
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0+03c <[^>]*> ee20 0b40 fnmuld d0, d0, d0
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0+040 <[^>]*> ee30 0b40 fsubd d0, d0, d0
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0+044 <[^>]*> ed90 0b00 fldd d0, \[r0\]
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0+048 <[^>]*> ed80 0b00 fstd d0, \[r0\]
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0+04c <[^>]*> ec90 0b02 fldmiad r0, {d0}
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0+050 <[^>]*> ec90 0b02 fldmiad r0, {d0}
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0+054 <[^>]*> ecb0 0b02 fldmiad r0!, {d0}
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0+058 <[^>]*> ecb0 0b02 fldmiad r0!, {d0}
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0+05c <[^>]*> ed30 0b02 fldmdbd r0!, {d0}
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0+060 <[^>]*> ed30 0b02 fldmdbd r0!, {d0}
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0+064 <[^>]*> ec80 0b02 fstmiad r0, {d0}
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0+068 <[^>]*> ec80 0b02 fstmiad r0, {d0}
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0+06c <[^>]*> eca0 0b02 fstmiad r0!, {d0}
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0+070 <[^>]*> eca0 0b02 fstmiad r0!, {d0}
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0+074 <[^>]*> ed20 0b02 fstmdbd r0!, {d0}
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0+078 <[^>]*> ed20 0b02 fstmdbd r0!, {d0}
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0+07c <[^>]*> eeb8 0bc0 fsitod d0, s0
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0+080 <[^>]*> eeb8 0b40 fuitod d0, s0
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0+084 <[^>]*> eebd 0b40 ftosid s0, d0
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0+088 <[^>]*> eebd 0bc0 ftosizd s0, d0
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0+08c <[^>]*> eebc 0b40 ftouid s0, d0
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0+090 <[^>]*> eebc 0bc0 ftouizd s0, d0
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0+094 <[^>]*> eeb7 0ac0 fcvtds d0, s0
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0+098 <[^>]*> eeb7 0bc0 fcvtsd s0, d0
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0+09c <[^>]*> ee30 0b10 fmrdh r0, d0
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0+0a0 <[^>]*> ee10 0b10 fmrdl r0, d0
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0+0a4 <[^>]*> ee20 0b10 fmdhr d0, r0
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0+0a8 <[^>]*> ee00 0b10 fmdlr d0, r0
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0+0ac <[^>]*> eeb5 1b40 fcmpzd d1
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0+0b0 <[^>]*> eeb5 2b40 fcmpzd d2
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0+0b4 <[^>]*> eeb5 fb40 fcmpzd d15
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0+0b8 <[^>]*> eeb4 0b41 fcmpd d0, d1
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0+0bc <[^>]*> eeb4 0b42 fcmpd d0, d2
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0+0c0 <[^>]*> eeb4 0b4f fcmpd d0, d15
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0+0c4 <[^>]*> eeb4 1b40 fcmpd d1, d0
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0+0c8 <[^>]*> eeb4 2b40 fcmpd d2, d0
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0+0cc <[^>]*> eeb4 fb40 fcmpd d15, d0
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0+0d0 <[^>]*> eeb4 5b4c fcmpd d5, d12
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0+0d4 <[^>]*> eeb1 0b41 fnegd d0, d1
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0+0d8 <[^>]*> eeb1 0b42 fnegd d0, d2
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0+0dc <[^>]*> eeb1 0b4f fnegd d0, d15
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0+0e0 <[^>]*> eeb1 1b40 fnegd d1, d0
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0+0e4 <[^>]*> eeb1 2b40 fnegd d2, d0
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0+0e8 <[^>]*> eeb1 fb40 fnegd d15, d0
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0+0ec <[^>]*> eeb1 cb45 fnegd d12, d5
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0+0f0 <[^>]*> ee30 0b01 faddd d0, d0, d1
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0+0f4 <[^>]*> ee30 0b02 faddd d0, d0, d2
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0+0f8 <[^>]*> ee30 0b0f faddd d0, d0, d15
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0+0fc <[^>]*> ee31 0b00 faddd d0, d1, d0
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0+100 <[^>]*> ee32 0b00 faddd d0, d2, d0
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0+104 <[^>]*> ee3f 0b00 faddd d0, d15, d0
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0+108 <[^>]*> ee30 1b00 faddd d1, d0, d0
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0+10c <[^>]*> ee30 2b00 faddd d2, d0, d0
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0+110 <[^>]*> ee30 fb00 faddd d15, d0, d0
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0+114 <[^>]*> ee39 cb05 faddd d12, d9, d5
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0+118 <[^>]*> eeb7 0ae0 fcvtds d0, s1
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0+11c <[^>]*> eeb7 0ac1 fcvtds d0, s2
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0+120 <[^>]*> eeb7 0aef fcvtds d0, s31
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0+124 <[^>]*> eeb7 1ac0 fcvtds d1, s0
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0+128 <[^>]*> eeb7 2ac0 fcvtds d2, s0
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0+12c <[^>]*> eeb7 fac0 fcvtds d15, s0
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0+130 <[^>]*> eef7 0bc0 fcvtsd s1, d0
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0+134 <[^>]*> eeb7 1bc0 fcvtsd s2, d0
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0+138 <[^>]*> eef7 fbc0 fcvtsd s31, d0
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0+13c <[^>]*> eeb7 0bc1 fcvtsd s0, d1
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0+140 <[^>]*> eeb7 0bc2 fcvtsd s0, d2
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0+144 <[^>]*> eeb7 0bcf fcvtsd s0, d15
|
||||
0+148 <[^>]*> ee30 1b10 fmrdh r1, d0
|
||||
0+14c <[^>]*> ee30 eb10 fmrdh lr, d0
|
||||
0+150 <[^>]*> ee31 0b10 fmrdh r0, d1
|
||||
0+154 <[^>]*> ee32 0b10 fmrdh r0, d2
|
||||
0+158 <[^>]*> ee3f 0b10 fmrdh r0, d15
|
||||
0+15c <[^>]*> ee10 1b10 fmrdl r1, d0
|
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0+160 <[^>]*> ee10 eb10 fmrdl lr, d0
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0+164 <[^>]*> ee11 0b10 fmrdl r0, d1
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||||
0+168 <[^>]*> ee12 0b10 fmrdl r0, d2
|
||||
0+16c <[^>]*> ee1f 0b10 fmrdl r0, d15
|
||||
0+170 <[^>]*> ee20 1b10 fmdhr d0, r1
|
||||
0+174 <[^>]*> ee20 eb10 fmdhr d0, lr
|
||||
0+178 <[^>]*> ee21 0b10 fmdhr d1, r0
|
||||
0+17c <[^>]*> ee22 0b10 fmdhr d2, r0
|
||||
0+180 <[^>]*> ee2f 0b10 fmdhr d15, r0
|
||||
0+184 <[^>]*> ee00 1b10 fmdlr d0, r1
|
||||
0+188 <[^>]*> ee00 eb10 fmdlr d0, lr
|
||||
0+18c <[^>]*> ee01 0b10 fmdlr d1, r0
|
||||
0+190 <[^>]*> ee02 0b10 fmdlr d2, r0
|
||||
0+194 <[^>]*> ee0f 0b10 fmdlr d15, r0
|
||||
0+198 <[^>]*> ed91 0b00 fldd d0, \[r1\]
|
||||
0+19c <[^>]*> ed9e 0b00 fldd d0, \[lr\]
|
||||
0+1a0 <[^>]*> ed90 0b00 fldd d0, \[r0\]
|
||||
0+1a4 <[^>]*> ed90 0bff fldd d0, \[r0, #1020\]
|
||||
0+1a8 <[^>]*> ed10 0bff fldd d0, \[r0, #-1020\]
|
||||
0+1ac <[^>]*> ed90 1b00 fldd d1, \[r0\]
|
||||
0+1b0 <[^>]*> ed90 2b00 fldd d2, \[r0\]
|
||||
0+1b4 <[^>]*> ed90 fb00 fldd d15, \[r0\]
|
||||
0+1b8 <[^>]*> ed8c cbc9 fstd d12, \[ip, #804\]
|
||||
0+1bc <[^>]*> ec90 1b02 fldmiad r0, {d1}
|
||||
0+1c0 <[^>]*> ec90 2b02 fldmiad r0, {d2}
|
||||
0+1c4 <[^>]*> ec90 fb02 fldmiad r0, {d15}
|
||||
0+1c8 <[^>]*> ec90 0b04 fldmiad r0, {d0-d1}
|
||||
0+1cc <[^>]*> ec90 0b06 fldmiad r0, {d0-d2}
|
||||
0+1d0 <[^>]*> ec90 0b20 fldmiad r0, {d0-d15}
|
||||
0+1d4 <[^>]*> ec90 1b1e fldmiad r0, {d1-d15}
|
||||
0+1d8 <[^>]*> ec90 2b1c fldmiad r0, {d2-d15}
|
||||
0+1dc <[^>]*> ec90 eb04 fldmiad r0, {d14-d15}
|
||||
0+1e0 <[^>]*> ec91 0b02 fldmiad r1, {d0}
|
||||
0+1e4 <[^>]*> ec9e 0b02 fldmiad lr, {d0}
|
||||
0+1e8 <[^>]*> eeb5 0b40 fcmpzd d0
|
||||
0+1ec <[^>]*> eeb5 1b40 fcmpzd d1
|
||||
0+1f0 <[^>]*> eeb5 2b40 fcmpzd d2
|
||||
0+1f4 <[^>]*> eeb5 3b40 fcmpzd d3
|
||||
0+1f8 <[^>]*> eeb5 4b40 fcmpzd d4
|
||||
0+1fc <[^>]*> eeb5 5b40 fcmpzd d5
|
||||
0+200 <[^>]*> eeb5 6b40 fcmpzd d6
|
||||
0+204 <[^>]*> eeb5 7b40 fcmpzd d7
|
||||
0+208 <[^>]*> eeb5 8b40 fcmpzd d8
|
||||
0+20c <[^>]*> eeb5 9b40 fcmpzd d9
|
||||
0+210 <[^>]*> eeb5 ab40 fcmpzd d10
|
||||
0+214 <[^>]*> eeb5 bb40 fcmpzd d11
|
||||
0+218 <[^>]*> eeb5 cb40 fcmpzd d12
|
||||
0+21c <[^>]*> eeb5 db40 fcmpzd d13
|
||||
0+220 <[^>]*> eeb5 eb40 fcmpzd d14
|
||||
0+224 <[^>]*> eeb5 fb40 fcmpzd d15
|
||||
# The "(eq|)" should be replaces by "eq" once the disassembler is fixed.
|
||||
0+228 <[^>]*> bf01 itttt eq
|
||||
0+22a <[^>]*> eeb4 1bcf fcmped(eq|) d1, d15
|
||||
0+22e <[^>]*> eeb5 2bc0 fcmpezd(eq|) d2
|
||||
0+232 <[^>]*> eeb4 3b4e fcmpd(eq|) d3, d14
|
||||
0+236 <[^>]*> eeb5 4b40 fcmpzd(eq|) d4
|
||||
0+23a <[^>]*> bf01 itttt eq
|
||||
0+23c <[^>]*> eeb0 5bcd fabsd(eq|) d5, d13
|
||||
0+240 <[^>]*> eeb0 6b4c fcpyd(eq|) d6, d12
|
||||
0+244 <[^>]*> eeb1 7b4b fnegd(eq|) d7, d11
|
||||
0+248 <[^>]*> eeb1 8bca fsqrtd(eq|) d8, d10
|
||||
0+24c <[^>]*> bf01 itttt eq
|
||||
0+24e <[^>]*> ee31 9b0f faddd(eq|) d9, d1, d15
|
||||
0+252 <[^>]*> ee83 2b0e fdivd(eq|) d2, d3, d14
|
||||
0+256 <[^>]*> ee0d 4b0c fmacd(eq|) d4, d13, d12
|
||||
0+25a <[^>]*> ee16 5b0b fmscd(eq|) d5, d6, d11
|
||||
0+25e <[^>]*> bf01 itttt eq
|
||||
0+260 <[^>]*> ee2a 7b09 fmuld(eq|) d7, d10, d9
|
||||
0+264 <[^>]*> ee09 8b4a fnmacd(eq|) d8, d9, d10
|
||||
0+268 <[^>]*> ee16 7b4b fnmscd(eq|) d7, d6, d11
|
||||
0+26c <[^>]*> ee24 5b4c fnmuld(eq|) d5, d4, d12
|
||||
0+270 <[^>]*> bf02 ittt eq
|
||||
0+272 <[^>]*> ee3d 3b4e fsubd(eq|) d3, d13, d14
|
||||
0+276 <[^>]*> ed95 2b00 fldd(eq|) d2, \[r5\]
|
||||
0+27a <[^>]*> ed8c 1b00 fstd(eq|) d1, \[ip\]
|
||||
0+27e <[^>]*> bf01 itttt eq
|
||||
0+280 <[^>]*> ec91 1b02 fldmiad(eq|) r1, {d1}
|
||||
0+284 <[^>]*> ec92 2b02 fldmiad(eq|) r2, {d2}
|
||||
0+288 <[^>]*> ecb3 3b02 fldmiad(eq|) r3!, {d3}
|
||||
0+28c <[^>]*> ecb4 4b02 fldmiad(eq|) r4!, {d4}
|
||||
0+290 <[^>]*> bf01 itttt eq
|
||||
0+292 <[^>]*> ed35 5b02 fldmdbd(eq|) r5!, {d5}
|
||||
0+296 <[^>]*> ed36 6b02 fldmdbd(eq|) r6!, {d6}
|
||||
0+29a <[^>]*> ec87 fb02 fstmiad(eq|) r7, {d15}
|
||||
0+29e <[^>]*> ec88 eb02 fstmiad(eq|) r8, {d14}
|
||||
0+2a2 <[^>]*> bf01 itttt eq
|
||||
0+2a4 <[^>]*> eca9 db02 fstmiad(eq|) r9!, {d13}
|
||||
0+2a8 <[^>]*> ecaa cb02 fstmiad(eq|) sl!, {d12}
|
||||
0+2ac <[^>]*> ed2b bb02 fstmdbd(eq|) fp!, {d11}
|
||||
0+2b0 <[^>]*> ed2c ab02 fstmdbd(eq|) ip!, {d10}
|
||||
0+2b4 <[^>]*> bf01 itttt eq
|
||||
0+2b6 <[^>]*> eeb8 fbe0 fsitod(eq|) d15, s1
|
||||
0+2ba <[^>]*> eeb8 1b6f fuitod(eq|) d1, s31
|
||||
0+2be <[^>]*> eefd 0b4f ftosid(eq|) s1, d15
|
||||
0+2c2 <[^>]*> eefd fbc2 ftosizd(eq|) s31, d2
|
||||
0+2c6 <[^>]*> bf01 itttt eq
|
||||
0+2c8 <[^>]*> eefc 7b42 ftouid(eq|) s15, d2
|
||||
0+2cc <[^>]*> eefc 5bc3 ftouizd(eq|) s11, d3
|
||||
0+2d0 <[^>]*> eeb7 1ac5 fcvtds(eq|) d1, s10
|
||||
0+2d4 <[^>]*> eef7 5bc1 fcvtsd(eq|) s11, d1
|
||||
0+2d8 <[^>]*> bf01 itttt eq
|
||||
0+2da <[^>]*> ee31 8b10 fmrdh(eq|) r8, d1
|
||||
0+2de <[^>]*> ee1f 7b10 fmrdl(eq|) r7, d15
|
||||
0+2e2 <[^>]*> ee21 fb10 fmdhr(eq|) d1, pc
|
||||
0+2e6 <[^>]*> ee0f 1b10 fmdlr(eq|) d15, r1
|
||||
0+2ea <[^>]*> bf00 nop
|
||||
0+2ec <[^>]*> bf00 nop
|
||||
0+2ee <[^>]*> bf00 nop
|
||||
298
gas/testsuite/gas/arm/vfp1_t2.s
Normal file
298
gas/testsuite/gas/arm/vfp1_t2.s
Normal file
@ -0,0 +1,298 @@
|
||||
@ VFP Instructions for D variants (Double precision)
|
||||
@ Same as vfp1.s, but for Thumb-2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.text
|
||||
.global F
|
||||
F:
|
||||
@ First we test the basic syntax and bit patterns of the opcodes.
|
||||
@ Most of these tests deliberatly use d0/r0 to avoid setting
|
||||
@ any more bits than necessary.
|
||||
|
||||
@ Comparison operations
|
||||
|
||||
fcmped d0, d0
|
||||
fcmpezd d0
|
||||
fcmpd d0, d0
|
||||
fcmpzd d0
|
||||
|
||||
@ Monadic data operations
|
||||
|
||||
fabsd d0, d0
|
||||
fcpyd d0, d0
|
||||
fnegd d0, d0
|
||||
fsqrtd d0, d0
|
||||
|
||||
@ Dyadic data operations
|
||||
|
||||
faddd d0, d0, d0
|
||||
fdivd d0, d0, d0
|
||||
fmacd d0, d0, d0
|
||||
fmscd d0, d0, d0
|
||||
fmuld d0, d0, d0
|
||||
fnmacd d0, d0, d0
|
||||
fnmscd d0, d0, d0
|
||||
fnmuld d0, d0, d0
|
||||
fsubd d0, d0, d0
|
||||
|
||||
@ Load/store operations
|
||||
|
||||
fldd d0, [r0]
|
||||
fstd d0, [r0]
|
||||
|
||||
@ Load/store multiple operations
|
||||
|
||||
fldmiad r0, {d0}
|
||||
fldmfdd r0, {d0}
|
||||
fldmiad r0!, {d0}
|
||||
fldmfdd r0!, {d0}
|
||||
fldmdbd r0!, {d0}
|
||||
fldmead r0!, {d0}
|
||||
|
||||
fstmiad r0, {d0}
|
||||
fstmead r0, {d0}
|
||||
fstmiad r0!, {d0}
|
||||
fstmead r0!, {d0}
|
||||
fstmdbd r0!, {d0}
|
||||
fstmfdd r0!, {d0}
|
||||
|
||||
@ Conversion operations
|
||||
|
||||
fsitod d0, s0
|
||||
fuitod d0, s0
|
||||
|
||||
ftosid s0, d0
|
||||
ftosizd s0, d0
|
||||
ftouid s0, d0
|
||||
ftouizd s0, d0
|
||||
|
||||
fcvtds d0, s0
|
||||
fcvtsd s0, d0
|
||||
|
||||
@ ARM from VFP operations
|
||||
|
||||
fmrdh r0, d0
|
||||
fmrdl r0, d0
|
||||
|
||||
@ VFP From ARM operations
|
||||
|
||||
fmdhr d0, r0
|
||||
fmdlr d0, r0
|
||||
|
||||
@ Now we test that the register fields are updated correctly for
|
||||
@ each class of instruction.
|
||||
|
||||
@ Single register operations (compare-zero):
|
||||
|
||||
fcmpzd d1
|
||||
fcmpzd d2
|
||||
fcmpzd d15
|
||||
|
||||
@ Two register comparison operations:
|
||||
|
||||
fcmpd d0, d1
|
||||
fcmpd d0, d2
|
||||
fcmpd d0, d15
|
||||
fcmpd d1, d0
|
||||
fcmpd d2, d0
|
||||
fcmpd d15, d0
|
||||
fcmpd d5, d12
|
||||
|
||||
@ Two register data operations (monadic)
|
||||
|
||||
fnegd d0, d1
|
||||
fnegd d0, d2
|
||||
fnegd d0, d15
|
||||
fnegd d1, d0
|
||||
fnegd d2, d0
|
||||
fnegd d15, d0
|
||||
fnegd d12, d5
|
||||
|
||||
@ Three register data operations (dyadic)
|
||||
|
||||
faddd d0, d0, d1
|
||||
faddd d0, d0, d2
|
||||
faddd d0, d0, d15
|
||||
faddd d0, d1, d0
|
||||
faddd d0, d2, d0
|
||||
faddd d0, d15, d0
|
||||
faddd d1, d0, d0
|
||||
faddd d2, d0, d0
|
||||
faddd d15, d0, d0
|
||||
faddd d12, d9, d5
|
||||
|
||||
@ Conversion operations
|
||||
|
||||
fcvtds d0, s1
|
||||
fcvtds d0, s2
|
||||
fcvtds d0, s31
|
||||
fcvtds d1, s0
|
||||
fcvtds d2, s0
|
||||
fcvtds d15, s0
|
||||
fcvtsd s1, d0
|
||||
fcvtsd s2, d0
|
||||
fcvtsd s31, d0
|
||||
fcvtsd s0, d1
|
||||
fcvtsd s0, d2
|
||||
fcvtsd s0, d15
|
||||
|
||||
@ Move to VFP from ARM
|
||||
|
||||
fmrdh r1, d0
|
||||
fmrdh r14, d0
|
||||
fmrdh r0, d1
|
||||
fmrdh r0, d2
|
||||
fmrdh r0, d15
|
||||
fmrdl r1, d0
|
||||
fmrdl r14, d0
|
||||
fmrdl r0, d1
|
||||
fmrdl r0, d2
|
||||
fmrdl r0, d15
|
||||
|
||||
@ Move to ARM from VFP
|
||||
|
||||
fmdhr d0, r1
|
||||
fmdhr d0, r14
|
||||
fmdhr d1, r0
|
||||
fmdhr d2, r0
|
||||
fmdhr d15, r0
|
||||
fmdlr d0, r1
|
||||
fmdlr d0, r14
|
||||
fmdlr d1, r0
|
||||
fmdlr d2, r0
|
||||
fmdlr d15, r0
|
||||
|
||||
@ Load/store operations
|
||||
|
||||
fldd d0, [r1]
|
||||
fldd d0, [r14]
|
||||
fldd d0, [r0, #0]
|
||||
fldd d0, [r0, #1020]
|
||||
fldd d0, [r0, #-1020]
|
||||
fldd d1, [r0]
|
||||
fldd d2, [r0]
|
||||
fldd d15, [r0]
|
||||
fstd d12, [r12, #804]
|
||||
|
||||
@ Load/store multiple operations
|
||||
|
||||
fldmiad r0, {d1}
|
||||
fldmiad r0, {d2}
|
||||
fldmiad r0, {d15}
|
||||
fldmiad r0, {d0-d1}
|
||||
fldmiad r0, {d0-d2}
|
||||
fldmiad r0, {d0-d15}
|
||||
fldmiad r0, {d1-d15}
|
||||
fldmiad r0, {d2-d15}
|
||||
fldmiad r0, {d14-d15}
|
||||
fldmiad r1, {d0}
|
||||
fldmiad r14, {d0}
|
||||
|
||||
@ Check that we assemble all the register names correctly
|
||||
|
||||
fcmpzd d0
|
||||
fcmpzd d1
|
||||
fcmpzd d2
|
||||
fcmpzd d3
|
||||
fcmpzd d4
|
||||
fcmpzd d5
|
||||
fcmpzd d6
|
||||
fcmpzd d7
|
||||
fcmpzd d8
|
||||
fcmpzd d9
|
||||
fcmpzd d10
|
||||
fcmpzd d11
|
||||
fcmpzd d12
|
||||
fcmpzd d13
|
||||
fcmpzd d14
|
||||
fcmpzd d15
|
||||
|
||||
@ Now we check the placement of the conditional execution substring.
|
||||
@ On VFP this is always at the end of the instruction.
|
||||
|
||||
@ Comparison operations
|
||||
|
||||
itttt eq
|
||||
fcmpedeq d1, d15
|
||||
fcmpezdeq d2
|
||||
fcmpdeq d3, d14
|
||||
fcmpzdeq d4
|
||||
|
||||
@ Monadic data operations
|
||||
|
||||
itttt eq
|
||||
fabsdeq d5, d13
|
||||
fcpydeq d6, d12
|
||||
fnegdeq d7, d11
|
||||
fsqrtdeq d8, d10
|
||||
|
||||
@ Dyadic data operations
|
||||
|
||||
itttt eq
|
||||
fadddeq d9, d1, d15
|
||||
fdivdeq d2, d3, d14
|
||||
fmacdeq d4, d13, d12
|
||||
fmscdeq d5, d6, d11
|
||||
itttt eq
|
||||
fmuldeq d7, d10, d9
|
||||
fnmacdeq d8, d9, d10
|
||||
fnmscdeq d7, d6, d11
|
||||
fnmuldeq d5, d4, d12
|
||||
ittt eq
|
||||
fsubdeq d3, d13, d14
|
||||
|
||||
@ Load/store operations
|
||||
|
||||
flddeq d2, [r5]
|
||||
fstdeq d1, [r12]
|
||||
|
||||
@ Load/store multiple operations
|
||||
|
||||
itttt eq
|
||||
fldmiadeq r1, {d1}
|
||||
fldmfddeq r2, {d2}
|
||||
fldmiadeq r3!, {d3}
|
||||
fldmfddeq r4!, {d4}
|
||||
itttt eq
|
||||
fldmdbdeq r5!, {d5}
|
||||
fldmeadeq r6!, {d6}
|
||||
|
||||
fstmiadeq r7, {d15}
|
||||
fstmeadeq r8, {d14}
|
||||
itttt eq
|
||||
fstmiadeq r9!, {d13}
|
||||
fstmeadeq r10!, {d12}
|
||||
fstmdbdeq r11!, {d11}
|
||||
fstmfddeq r12!, {d10}
|
||||
|
||||
@ Conversion operations
|
||||
|
||||
itttt eq
|
||||
fsitodeq d15, s1
|
||||
fuitodeq d1, s31
|
||||
|
||||
ftosideq s1, d15
|
||||
ftosizdeq s31, d2
|
||||
itttt eq
|
||||
ftouideq s15, d2
|
||||
ftouizdeq s11, d3
|
||||
|
||||
fcvtdseq d1, s10
|
||||
fcvtsdeq s11, d1
|
||||
|
||||
@ ARM from VFP operations
|
||||
|
||||
itttt eq
|
||||
fmrdheq r8, d1
|
||||
fmrdleq r7, d15
|
||||
|
||||
@ VFP From ARM operations
|
||||
|
||||
fmdhreq d1, r15
|
||||
fmdlreq d15, r1
|
||||
|
||||
# Add three nop instructions to ensure that the
|
||||
# output is 32-byte aligned as required for arm-aout.
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
258
gas/testsuite/gas/arm/vfp1xD_t2.d
Normal file
258
gas/testsuite/gas/arm/vfp1xD_t2.d
Normal file
@ -0,0 +1,258 @@
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: Thumb-2 VFP Single-precision instructions
|
||||
#as: -mfpu=vfpxd
|
||||
|
||||
# Test the ARM VFP Single Precision instructions
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+000 <[^>]*> eef1 fa10 fmstat
|
||||
0+004 <[^>]*> eeb4 0ac0 fcmpes s0, s0
|
||||
0+008 <[^>]*> eeb5 0ac0 fcmpezs s0
|
||||
0+00c <[^>]*> eeb4 0a40 fcmps s0, s0
|
||||
0+010 <[^>]*> eeb5 0a40 fcmpzs s0
|
||||
0+014 <[^>]*> eeb0 0ac0 fabss s0, s0
|
||||
0+018 <[^>]*> eeb0 0a40 fcpys s0, s0
|
||||
0+01c <[^>]*> eeb1 0a40 fnegs s0, s0
|
||||
0+020 <[^>]*> eeb1 0ac0 fsqrts s0, s0
|
||||
0+024 <[^>]*> ee30 0a00 fadds s0, s0, s0
|
||||
0+028 <[^>]*> ee80 0a00 fdivs s0, s0, s0
|
||||
0+02c <[^>]*> ee00 0a00 fmacs s0, s0, s0
|
||||
0+030 <[^>]*> ee10 0a00 fmscs s0, s0, s0
|
||||
0+034 <[^>]*> ee20 0a00 fmuls s0, s0, s0
|
||||
0+038 <[^>]*> ee00 0a40 fnmacs s0, s0, s0
|
||||
0+03c <[^>]*> ee10 0a40 fnmscs s0, s0, s0
|
||||
0+040 <[^>]*> ee20 0a40 fnmuls s0, s0, s0
|
||||
0+044 <[^>]*> ee30 0a40 fsubs s0, s0, s0
|
||||
0+048 <[^>]*> ed90 0a00 flds s0, \[r0\]
|
||||
0+04c <[^>]*> ed80 0a00 fsts s0, \[r0\]
|
||||
0+050 <[^>]*> ec90 0a01 fldmias r0, {s0}
|
||||
0+054 <[^>]*> ec90 0a01 fldmias r0, {s0}
|
||||
0+058 <[^>]*> ecb0 0a01 fldmias r0!, {s0}
|
||||
0+05c <[^>]*> ecb0 0a01 fldmias r0!, {s0}
|
||||
0+060 <[^>]*> ed30 0a01 fldmdbs r0!, {s0}
|
||||
0+064 <[^>]*> ed30 0a01 fldmdbs r0!, {s0}
|
||||
0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}
|
||||
0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}
|
||||
0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}
|
||||
0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}
|
||||
0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}
|
||||
0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}
|
||||
0+080 <[^>]*> ec80 0a01 fstmias r0, {s0}
|
||||
0+084 <[^>]*> ec80 0a01 fstmias r0, {s0}
|
||||
0+088 <[^>]*> eca0 0a01 fstmias r0!, {s0}
|
||||
0+08c <[^>]*> eca0 0a01 fstmias r0!, {s0}
|
||||
0+090 <[^>]*> ed20 0a01 fstmdbs r0!, {s0}
|
||||
0+094 <[^>]*> ed20 0a01 fstmdbs r0!, {s0}
|
||||
0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}
|
||||
0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}
|
||||
0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}
|
||||
0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}
|
||||
0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}
|
||||
0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}
|
||||
0+0b0 <[^>]*> eeb8 0ac0 fsitos s0, s0
|
||||
0+0b4 <[^>]*> eeb8 0a40 fuitos s0, s0
|
||||
0+0b8 <[^>]*> eebd 0a40 ftosis s0, s0
|
||||
0+0bc <[^>]*> eebd 0ac0 ftosizs s0, s0
|
||||
0+0c0 <[^>]*> eebc 0a40 ftouis s0, s0
|
||||
0+0c4 <[^>]*> eebc 0ac0 ftouizs s0, s0
|
||||
0+0c8 <[^>]*> ee10 0a10 fmrs r0, s0
|
||||
0+0cc <[^>]*> eef0 0a10 fmrx r0, fpsid
|
||||
0+0d0 <[^>]*> eef1 0a10 fmrx r0, fpscr
|
||||
0+0d4 <[^>]*> eef8 0a10 fmrx r0, fpexc
|
||||
0+0d8 <[^>]*> ee00 0a10 fmsr s0, r0
|
||||
0+0dc <[^>]*> eee0 0a10 fmxr fpsid, r0
|
||||
0+0e0 <[^>]*> eee1 0a10 fmxr fpscr, r0
|
||||
0+0e4 <[^>]*> eee8 0a10 fmxr fpexc, r0
|
||||
0+0e8 <[^>]*> eef5 0a40 fcmpzs s1
|
||||
0+0ec <[^>]*> eeb5 1a40 fcmpzs s2
|
||||
0+0f0 <[^>]*> eef5 fa40 fcmpzs s31
|
||||
0+0f4 <[^>]*> eeb4 0a60 fcmps s0, s1
|
||||
0+0f8 <[^>]*> eeb4 0a41 fcmps s0, s2
|
||||
0+0fc <[^>]*> eeb4 0a6f fcmps s0, s31
|
||||
0+100 <[^>]*> eef4 0a40 fcmps s1, s0
|
||||
0+104 <[^>]*> eeb4 1a40 fcmps s2, s0
|
||||
0+108 <[^>]*> eef4 fa40 fcmps s31, s0
|
||||
0+10c <[^>]*> eef4 aa46 fcmps s21, s12
|
||||
0+110 <[^>]*> eeb1 0a60 fnegs s0, s1
|
||||
0+114 <[^>]*> eeb1 0a41 fnegs s0, s2
|
||||
0+118 <[^>]*> eeb1 0a6f fnegs s0, s31
|
||||
0+11c <[^>]*> eef1 0a40 fnegs s1, s0
|
||||
0+120 <[^>]*> eeb1 1a40 fnegs s2, s0
|
||||
0+124 <[^>]*> eef1 fa40 fnegs s31, s0
|
||||
0+128 <[^>]*> eeb1 6a6a fnegs s12, s21
|
||||
0+12c <[^>]*> ee30 0a20 fadds s0, s0, s1
|
||||
0+130 <[^>]*> ee30 0a01 fadds s0, s0, s2
|
||||
0+134 <[^>]*> ee30 0a2f fadds s0, s0, s31
|
||||
0+138 <[^>]*> ee30 0a80 fadds s0, s1, s0
|
||||
0+13c <[^>]*> ee31 0a00 fadds s0, s2, s0
|
||||
0+140 <[^>]*> ee3f 0a80 fadds s0, s31, s0
|
||||
0+144 <[^>]*> ee70 0a00 fadds s1, s0, s0
|
||||
0+148 <[^>]*> ee30 1a00 fadds s2, s0, s0
|
||||
0+14c <[^>]*> ee70 fa00 fadds s31, s0, s0
|
||||
0+150 <[^>]*> ee3a 6aa2 fadds s12, s21, s5
|
||||
0+154 <[^>]*> eeb8 0ae0 fsitos s0, s1
|
||||
0+158 <[^>]*> eeb8 0ac1 fsitos s0, s2
|
||||
0+15c <[^>]*> eeb8 0aef fsitos s0, s31
|
||||
0+160 <[^>]*> eef8 0ac0 fsitos s1, s0
|
||||
0+164 <[^>]*> eeb8 1ac0 fsitos s2, s0
|
||||
0+168 <[^>]*> eef8 fac0 fsitos s31, s0
|
||||
0+16c <[^>]*> eebd 0a60 ftosis s0, s1
|
||||
0+170 <[^>]*> eebd 0a41 ftosis s0, s2
|
||||
0+174 <[^>]*> eebd 0a6f ftosis s0, s31
|
||||
0+178 <[^>]*> eefd 0a40 ftosis s1, s0
|
||||
0+17c <[^>]*> eebd 1a40 ftosis s2, s0
|
||||
0+180 <[^>]*> eefd fa40 ftosis s31, s0
|
||||
0+184 <[^>]*> ee00 1a10 fmsr s0, r1
|
||||
0+188 <[^>]*> ee00 7a10 fmsr s0, r7
|
||||
0+18c <[^>]*> ee00 ea10 fmsr s0, lr
|
||||
0+190 <[^>]*> ee00 0a90 fmsr s1, r0
|
||||
0+194 <[^>]*> ee01 0a10 fmsr s2, r0
|
||||
0+198 <[^>]*> ee0f 0a90 fmsr s31, r0
|
||||
0+19c <[^>]*> ee0a 7a90 fmsr s21, r7
|
||||
0+1a0 <[^>]*> eee0 1a10 fmxr fpsid, r1
|
||||
0+1a4 <[^>]*> eee0 ea10 fmxr fpsid, lr
|
||||
0+1a8 <[^>]*> ee10 0a90 fmrs r0, s1
|
||||
0+1ac <[^>]*> ee11 0a10 fmrs r0, s2
|
||||
0+1b0 <[^>]*> ee1f 0a90 fmrs r0, s31
|
||||
0+1b4 <[^>]*> ee10 1a10 fmrs r1, s0
|
||||
0+1b8 <[^>]*> ee10 7a10 fmrs r7, s0
|
||||
0+1bc <[^>]*> ee10 ea10 fmrs lr, s0
|
||||
0+1c0 <[^>]*> ee15 9a90 fmrs r9, s11
|
||||
0+1c4 <[^>]*> eef0 1a10 fmrx r1, fpsid
|
||||
0+1c8 <[^>]*> eef0 ea10 fmrx lr, fpsid
|
||||
0+1cc <[^>]*> ed91 0a00 flds s0, \[r1\]
|
||||
0+1d0 <[^>]*> ed9e 0a00 flds s0, \[lr\]
|
||||
0+1d4 <[^>]*> ed90 0a00 flds s0, \[r0\]
|
||||
0+1d8 <[^>]*> ed90 0aff flds s0, \[r0, #1020\]
|
||||
0+1dc <[^>]*> ed10 0aff flds s0, \[r0, #-1020\]
|
||||
0+1e0 <[^>]*> edd0 0a00 flds s1, \[r0\]
|
||||
0+1e4 <[^>]*> ed90 1a00 flds s2, \[r0\]
|
||||
0+1e8 <[^>]*> edd0 fa00 flds s31, \[r0\]
|
||||
0+1ec <[^>]*> edcc aac9 fsts s21, \[ip, #804\]
|
||||
0+1f0 <[^>]*> ecd0 0a01 fldmias r0, {s1}
|
||||
0+1f4 <[^>]*> ec90 1a01 fldmias r0, {s2}
|
||||
0+1f8 <[^>]*> ecd0 fa01 fldmias r0, {s31}
|
||||
0+1fc <[^>]*> ec90 0a02 fldmias r0, {s0-s1}
|
||||
0+200 <[^>]*> ec90 0a03 fldmias r0, {s0-s2}
|
||||
0+204 <[^>]*> ec90 0a20 fldmias r0, {s0-s31}
|
||||
0+208 <[^>]*> ecd0 0a1f fldmias r0, {s1-s31}
|
||||
0+20c <[^>]*> ec90 1a1e fldmias r0, {s2-s31}
|
||||
0+210 <[^>]*> ec90 fa02 fldmias r0, {s30-s31}
|
||||
0+214 <[^>]*> ec91 0a01 fldmias r1, {s0}
|
||||
0+218 <[^>]*> ec9e 0a01 fldmias lr, {s0}
|
||||
0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}
|
||||
0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}
|
||||
0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}
|
||||
0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}
|
||||
0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}
|
||||
0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}
|
||||
0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}
|
||||
0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}
|
||||
0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}
|
||||
0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}
|
||||
0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}
|
||||
0+248 <[^>]*> eeb5 0a40 fcmpzs s0
|
||||
0+24c <[^>]*> eef5 0a40 fcmpzs s1
|
||||
0+250 <[^>]*> eeb5 1a40 fcmpzs s2
|
||||
0+254 <[^>]*> eef5 1a40 fcmpzs s3
|
||||
0+258 <[^>]*> eeb5 2a40 fcmpzs s4
|
||||
0+25c <[^>]*> eef5 2a40 fcmpzs s5
|
||||
0+260 <[^>]*> eeb5 3a40 fcmpzs s6
|
||||
0+264 <[^>]*> eef5 3a40 fcmpzs s7
|
||||
0+268 <[^>]*> eeb5 4a40 fcmpzs s8
|
||||
0+26c <[^>]*> eef5 4a40 fcmpzs s9
|
||||
0+270 <[^>]*> eeb5 5a40 fcmpzs s10
|
||||
0+274 <[^>]*> eef5 5a40 fcmpzs s11
|
||||
0+278 <[^>]*> eeb5 6a40 fcmpzs s12
|
||||
0+27c <[^>]*> eef5 6a40 fcmpzs s13
|
||||
0+280 <[^>]*> eeb5 7a40 fcmpzs s14
|
||||
0+284 <[^>]*> eef5 7a40 fcmpzs s15
|
||||
0+288 <[^>]*> eeb5 8a40 fcmpzs s16
|
||||
0+28c <[^>]*> eef5 8a40 fcmpzs s17
|
||||
0+290 <[^>]*> eeb5 9a40 fcmpzs s18
|
||||
0+294 <[^>]*> eef5 9a40 fcmpzs s19
|
||||
0+298 <[^>]*> eeb5 aa40 fcmpzs s20
|
||||
0+29c <[^>]*> eef5 aa40 fcmpzs s21
|
||||
0+2a0 <[^>]*> eeb5 ba40 fcmpzs s22
|
||||
0+2a4 <[^>]*> eef5 ba40 fcmpzs s23
|
||||
0+2a8 <[^>]*> eeb5 ca40 fcmpzs s24
|
||||
0+2ac <[^>]*> eef5 ca40 fcmpzs s25
|
||||
0+2b0 <[^>]*> eeb5 da40 fcmpzs s26
|
||||
0+2b4 <[^>]*> eef5 da40 fcmpzs s27
|
||||
0+2b8 <[^>]*> eeb5 ea40 fcmpzs s28
|
||||
0+2bc <[^>]*> eef5 ea40 fcmpzs s29
|
||||
0+2c0 <[^>]*> eeb5 fa40 fcmpzs s30
|
||||
0+2c4 <[^>]*> eef5 fa40 fcmpzs s31
|
||||
# The "(eq|)" should be replaces by "eq" once the disassembler is fixed.
|
||||
0+2c8 <[^>]*> bf01 itttt eq
|
||||
0+2ca <[^>]*> eef1 fa10 fmstat(eq|)
|
||||
0+2ce <[^>]*> eef4 1ae3 fcmpes(eq|) s3, s7
|
||||
0+2d2 <[^>]*> eef5 2ac0 fcmpezs(eq|) s5
|
||||
0+2d6 <[^>]*> eef4 0a41 fcmps(eq|) s1, s2
|
||||
0+2da <[^>]*> bf01 itttt eq
|
||||
0+2dc <[^>]*> eef5 0a40 fcmpzs(eq|) s1
|
||||
0+2e0 <[^>]*> eef0 0ae1 fabss(eq|) s1, s3
|
||||
0+2e4 <[^>]*> eef0 fa69 fcpys(eq|) s31, s19
|
||||
0+2e8 <[^>]*> eeb1 aa44 fnegs(eq|) s20, s8
|
||||
0+2ec <[^>]*> bf01 itttt eq
|
||||
0+2ee <[^>]*> eef1 2ae3 fsqrts(eq|) s5, s7
|
||||
0+2f2 <[^>]*> ee32 3a82 fadds(eq|) s6, s5, s4
|
||||
0+2f6 <[^>]*> eec1 1a20 fdivs(eq|) s3, s2, s1
|
||||
0+2fa <[^>]*> ee4f fa2e fmacs(eq|) s31, s30, s29
|
||||
0+2fe <[^>]*> bf01 itttt eq
|
||||
0+300 <[^>]*> ee1d ea8d fmscs(eq|) s28, s27, s26
|
||||
0+304 <[^>]*> ee6c ca2b fmuls(eq|) s25, s24, s23
|
||||
0+308 <[^>]*> ee0a baca fnmacs(eq|) s22, s21, s20
|
||||
0+30c <[^>]*> ee59 9a68 fnmscs(eq|) s19, s18, s17
|
||||
0+310 <[^>]*> bf01 itttt eq
|
||||
0+312 <[^>]*> ee27 8ac7 fnmuls(eq|) s16, s15, s14
|
||||
0+316 <[^>]*> ee76 6a65 fsubs(eq|) s13, s12, s11
|
||||
0+31a <[^>]*> ed98 5a00 flds(eq|) s10, \[r8\]
|
||||
0+31e <[^>]*> edc7 4a00 fsts(eq|) s9, \[r7\]
|
||||
0+322 <[^>]*> bf01 itttt eq
|
||||
0+324 <[^>]*> ec91 4a01 fldmias(eq|) r1, {s8}
|
||||
0+328 <[^>]*> ecd2 3a01 fldmias(eq|) r2, {s7}
|
||||
0+32c <[^>]*> ecb3 3a01 fldmias(eq|) r3!, {s6}
|
||||
0+330 <[^>]*> ecf4 2a01 fldmias(eq|) r4!, {s5}
|
||||
0+334 <[^>]*> bf01 itttt eq
|
||||
0+336 <[^>]*> ed35 2a01 fldmdbs(eq|) r5!, {s4}
|
||||
0+33a <[^>]*> ed76 1a01 fldmdbs(eq|) r6!, {s3}
|
||||
0+33e <[^>]*> ec97 1b03 fldmiax(eq|) r7, {d1}
|
||||
0+342 <[^>]*> ec98 2b03 fldmiax(eq|) r8, {d2}
|
||||
0+346 <[^>]*> bf01 itttt eq
|
||||
0+348 <[^>]*> ecb9 3b03 fldmiax(eq|) r9!, {d3}
|
||||
0+34c <[^>]*> ecba 4b03 fldmiax(eq|) sl!, {d4}
|
||||
0+350 <[^>]*> ed3b 5b03 fldmdbx(eq|) fp!, {d5}
|
||||
0+354 <[^>]*> ed3c 6b03 fldmdbx(eq|) ip!, {d6}
|
||||
0+358 <[^>]*> bf01 itttt eq
|
||||
0+35a <[^>]*> ec8d 1a01 fstmias(eq|) sp, {s2}
|
||||
0+35e <[^>]*> ecce 0a01 fstmias(eq|) lr, {s1}
|
||||
0+362 <[^>]*> ece1 fa01 fstmias(eq|) r1!, {s31}
|
||||
0+366 <[^>]*> eca2 fa01 fstmias(eq|) r2!, {s30}
|
||||
0+36a <[^>]*> bf01 itttt eq
|
||||
0+36c <[^>]*> ed63 ea01 fstmdbs(eq|) r3!, {s29}
|
||||
0+370 <[^>]*> ed24 ea01 fstmdbs(eq|) r4!, {s28}
|
||||
0+374 <[^>]*> ec85 7b03 fstmiax(eq|) r5, {d7}
|
||||
0+378 <[^>]*> ec86 8b03 fstmiax(eq|) r6, {d8}
|
||||
0+37c <[^>]*> bf01 itttt eq
|
||||
0+37e <[^>]*> eca7 9b03 fstmiax(eq|) r7!, {d9}
|
||||
0+382 <[^>]*> eca8 ab03 fstmiax(eq|) r8!, {d10}
|
||||
0+386 <[^>]*> ed29 bb03 fstmdbx(eq|) r9!, {d11}
|
||||
0+38a <[^>]*> ed2a cb03 fstmdbx(eq|) sl!, {d12}
|
||||
0+38e <[^>]*> bf01 itttt eq
|
||||
0+390 <[^>]*> eef8 dac3 fsitos(eq|) s27, s6
|
||||
0+394 <[^>]*> eefd ca62 ftosis(eq|) s25, s5
|
||||
0+398 <[^>]*> eefd bac2 ftosizs(eq|) s23, s4
|
||||
0+39c <[^>]*> eefc aa61 ftouis(eq|) s21, s3
|
||||
0+3a0 <[^>]*> bf01 itttt eq
|
||||
0+3a2 <[^>]*> eefc 9ac1 ftouizs(eq|) s19, s2
|
||||
0+3a6 <[^>]*> eef8 8a60 fuitos(eq|) s17, s1
|
||||
0+3aa <[^>]*> ee11 ba90 fmrs(eq|) fp, s3
|
||||
0+3ae <[^>]*> eef0 9a10 fmrx(eq|) r9, fpsid
|
||||
0+3b2 <[^>]*> bf04 itt eq
|
||||
0+3b4 <[^>]*> ee01 9a90 fmsr(eq|) s3, r9
|
||||
0+3b8 <[^>]*> eee0 8a10 fmxr(eq|) fpsid, r8
|
||||
0+3bc <[^>]*> bf00 nop
|
||||
0+3be <[^>]*> bf00 nop
|
||||
359
gas/testsuite/gas/arm/vfp1xD_t2.s
Normal file
359
gas/testsuite/gas/arm/vfp1xD_t2.s
Normal file
@ -0,0 +1,359 @@
|
||||
@ VFP Instructions for v1xD variants (Single precision only)
|
||||
@ Same as vfp1xD.s, but for Thumb-2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.text
|
||||
.global F
|
||||
F:
|
||||
@ First we test the basic syntax and bit patterns of the opcodes.
|
||||
@ Most of these tests deliberatly use s0/r0 to avoid setting
|
||||
@ any more bits than necessary.
|
||||
|
||||
@ Comparison operations
|
||||
|
||||
fmstat
|
||||
|
||||
fcmpes s0, s0
|
||||
fcmpezs s0
|
||||
fcmps s0, s0
|
||||
fcmpzs s0
|
||||
|
||||
@ Monadic data operations
|
||||
|
||||
fabss s0, s0
|
||||
fcpys s0, s0
|
||||
fnegs s0, s0
|
||||
fsqrts s0, s0
|
||||
|
||||
@ Dyadic data operations
|
||||
|
||||
fadds s0, s0, s0
|
||||
fdivs s0, s0, s0
|
||||
fmacs s0, s0, s0
|
||||
fmscs s0, s0, s0
|
||||
fmuls s0, s0, s0
|
||||
fnmacs s0, s0, s0
|
||||
fnmscs s0, s0, s0
|
||||
fnmuls s0, s0, s0
|
||||
fsubs s0, s0, s0
|
||||
|
||||
@ Load/store operations
|
||||
|
||||
flds s0, [r0]
|
||||
fsts s0, [r0]
|
||||
|
||||
@ Load/store multiple operations
|
||||
|
||||
fldmias r0, {s0}
|
||||
fldmfds r0, {s0}
|
||||
fldmias r0!, {s0}
|
||||
fldmfds r0!, {s0}
|
||||
fldmdbs r0!, {s0}
|
||||
fldmeas r0!, {s0}
|
||||
|
||||
fldmiax r0, {d0}
|
||||
fldmfdx r0, {d0}
|
||||
fldmiax r0!, {d0}
|
||||
fldmfdx r0!, {d0}
|
||||
fldmdbx r0!, {d0}
|
||||
fldmeax r0!, {d0}
|
||||
|
||||
fstmias r0, {s0}
|
||||
fstmeas r0, {s0}
|
||||
fstmias r0!, {s0}
|
||||
fstmeas r0!, {s0}
|
||||
fstmdbs r0!, {s0}
|
||||
fstmfds r0!, {s0}
|
||||
|
||||
fstmiax r0, {d0}
|
||||
fstmeax r0, {d0}
|
||||
fstmiax r0!, {d0}
|
||||
fstmeax r0!, {d0}
|
||||
fstmdbx r0!, {d0}
|
||||
fstmfdx r0!, {d0}
|
||||
|
||||
@ Conversion operations
|
||||
|
||||
fsitos s0, s0
|
||||
fuitos s0, s0
|
||||
|
||||
ftosis s0, s0
|
||||
ftosizs s0, s0
|
||||
ftouis s0, s0
|
||||
ftouizs s0, s0
|
||||
|
||||
@ ARM from VFP operations
|
||||
|
||||
fmrs r0, s0
|
||||
fmrx r0, fpsid
|
||||
fmrx r0, fpscr
|
||||
fmrx r0, fpexc
|
||||
|
||||
@ VFP From ARM operations
|
||||
|
||||
fmsr s0, r0
|
||||
fmxr fpsid, r0
|
||||
fmxr fpscr, r0
|
||||
fmxr fpexc, r0
|
||||
|
||||
@ Now we test that the register fields are updated correctly for
|
||||
@ each class of instruction.
|
||||
|
||||
@ Single register operations (compare-zero):
|
||||
|
||||
fcmpzs s1
|
||||
fcmpzs s2
|
||||
fcmpzs s31
|
||||
|
||||
@ Two register comparison operations:
|
||||
|
||||
fcmps s0, s1
|
||||
fcmps s0, s2
|
||||
fcmps s0, s31
|
||||
fcmps s1, s0
|
||||
fcmps s2, s0
|
||||
fcmps s31, s0
|
||||
fcmps s21, s12
|
||||
|
||||
@ Two register data operations (monadic)
|
||||
|
||||
fnegs s0, s1
|
||||
fnegs s0, s2
|
||||
fnegs s0, s31
|
||||
fnegs s1, s0
|
||||
fnegs s2, s0
|
||||
fnegs s31, s0
|
||||
fnegs s12, s21
|
||||
|
||||
@ Three register data operations (dyadic)
|
||||
|
||||
fadds s0, s0, s1
|
||||
fadds s0, s0, s2
|
||||
fadds s0, s0, s31
|
||||
fadds s0, s1, s0
|
||||
fadds s0, s2, s0
|
||||
fadds s0, s31, s0
|
||||
fadds s1, s0, s0
|
||||
fadds s2, s0, s0
|
||||
fadds s31, s0, s0
|
||||
fadds s12, s21, s5
|
||||
|
||||
@ Conversion operations
|
||||
|
||||
fsitos s0, s1
|
||||
fsitos s0, s2
|
||||
fsitos s0, s31
|
||||
fsitos s1, s0
|
||||
fsitos s2, s0
|
||||
fsitos s31, s0
|
||||
|
||||
ftosis s0, s1
|
||||
ftosis s0, s2
|
||||
ftosis s0, s31
|
||||
ftosis s1, s0
|
||||
ftosis s2, s0
|
||||
ftosis s31, s0
|
||||
|
||||
@ Move to VFP from ARM
|
||||
|
||||
fmsr s0, r1
|
||||
fmsr s0, r7
|
||||
fmsr s0, r14
|
||||
fmsr s1, r0
|
||||
fmsr s2, r0
|
||||
fmsr s31, r0
|
||||
fmsr s21, r7
|
||||
|
||||
fmxr fpsid, r1
|
||||
fmxr fpsid, r14
|
||||
|
||||
@ Move to ARM from VFP
|
||||
|
||||
fmrs r0, s1
|
||||
fmrs r0, s2
|
||||
fmrs r0, s31
|
||||
fmrs r1, s0
|
||||
fmrs r7, s0
|
||||
fmrs r14, s0
|
||||
fmrs r9, s11
|
||||
|
||||
fmrx r1, fpsid
|
||||
fmrx r14, fpsid
|
||||
|
||||
@ Load/store operations
|
||||
|
||||
flds s0, [r1]
|
||||
flds s0, [r14]
|
||||
flds s0, [r0, #0]
|
||||
flds s0, [r0, #1020]
|
||||
flds s0, [r0, #-1020]
|
||||
flds s1, [r0]
|
||||
flds s2, [r0]
|
||||
flds s31, [r0]
|
||||
fsts s21, [r12, #804]
|
||||
|
||||
@ Load/store multiple operations
|
||||
|
||||
fldmias r0, {s1}
|
||||
fldmias r0, {s2}
|
||||
fldmias r0, {s31}
|
||||
fldmias r0, {s0-s1}
|
||||
fldmias r0, {s0-s2}
|
||||
fldmias r0, {s0-s31}
|
||||
fldmias r0, {s1-s31}
|
||||
fldmias r0, {s2-s31}
|
||||
fldmias r0, {s30-s31}
|
||||
fldmias r1, {s0}
|
||||
fldmias r14, {s0}
|
||||
|
||||
fstmiax r0, {d1}
|
||||
fstmiax r0, {d2}
|
||||
fstmiax r0, {d15}
|
||||
fstmiax r0, {d0-d1}
|
||||
fstmiax r0, {d0-d2}
|
||||
fstmiax r0, {d0-d15}
|
||||
fstmiax r0, {d1-d15}
|
||||
fstmiax r0, {d2-d15}
|
||||
fstmiax r0, {d14-d15}
|
||||
fstmiax r1, {d0}
|
||||
fstmiax r14, {d0}
|
||||
|
||||
@ Check that we assemble all the register names correctly
|
||||
|
||||
fcmpzs s0
|
||||
fcmpzs s1
|
||||
fcmpzs s2
|
||||
fcmpzs s3
|
||||
fcmpzs s4
|
||||
fcmpzs s5
|
||||
fcmpzs s6
|
||||
fcmpzs s7
|
||||
fcmpzs s8
|
||||
fcmpzs s9
|
||||
fcmpzs s10
|
||||
fcmpzs s11
|
||||
fcmpzs s12
|
||||
fcmpzs s13
|
||||
fcmpzs s14
|
||||
fcmpzs s15
|
||||
fcmpzs s16
|
||||
fcmpzs s17
|
||||
fcmpzs s18
|
||||
fcmpzs s19
|
||||
fcmpzs s20
|
||||
fcmpzs s21
|
||||
fcmpzs s22
|
||||
fcmpzs s23
|
||||
fcmpzs s24
|
||||
fcmpzs s25
|
||||
fcmpzs s26
|
||||
fcmpzs s27
|
||||
fcmpzs s28
|
||||
fcmpzs s29
|
||||
fcmpzs s30
|
||||
fcmpzs s31
|
||||
|
||||
@ Now we check the placement of the conditional execution substring.
|
||||
@ On VFP this is always at the end of the instruction.
|
||||
@ We use different register numbers here to check for correct
|
||||
@ disassembly
|
||||
|
||||
@ Comparison operations
|
||||
|
||||
itttt eq
|
||||
fmstateq
|
||||
|
||||
fcmpeseq s3, s7
|
||||
fcmpezseq s5
|
||||
fcmpseq s1, s2
|
||||
itttt eq
|
||||
fcmpzseq s1
|
||||
|
||||
@ Monadic data operations
|
||||
|
||||
fabsseq s1, s3
|
||||
fcpyseq s31, s19
|
||||
fnegseq s20, s8
|
||||
itttt eq
|
||||
fsqrtseq s5, s7
|
||||
|
||||
@ Dyadic data operations
|
||||
|
||||
faddseq s6, s5, s4
|
||||
fdivseq s3, s2, s1
|
||||
fmacseq s31, s30, s29
|
||||
itttt eq
|
||||
fmscseq s28, s27, s26
|
||||
fmulseq s25, s24, s23
|
||||
fnmacseq s22, s21, s20
|
||||
fnmscseq s19, s18, s17
|
||||
itttt eq
|
||||
fnmulseq s16, s15, s14
|
||||
fsubseq s13, s12, s11
|
||||
|
||||
@ Load/store operations
|
||||
|
||||
fldseq s10, [r8]
|
||||
fstseq s9, [r7]
|
||||
|
||||
@ Load/store multiple operations
|
||||
|
||||
itttt eq
|
||||
fldmiaseq r1, {s8}
|
||||
fldmfdseq r2, {s7}
|
||||
fldmiaseq r3!, {s6}
|
||||
fldmfdseq r4!, {s5}
|
||||
itttt eq
|
||||
fldmdbseq r5!, {s4}
|
||||
fldmeaseq r6!, {s3}
|
||||
|
||||
fldmiaxeq r7, {d1}
|
||||
fldmfdxeq r8, {d2}
|
||||
itttt eq
|
||||
fldmiaxeq r9!, {d3}
|
||||
fldmfdxeq r10!, {d4}
|
||||
fldmdbxeq r11!, {d5}
|
||||
fldmeaxeq r12!, {d6}
|
||||
|
||||
itttt eq
|
||||
fstmiaseq r13, {s2}
|
||||
fstmeaseq r14, {s1}
|
||||
fstmiaseq r1!, {s31}
|
||||
fstmeaseq r2!, {s30}
|
||||
itttt eq
|
||||
fstmdbseq r3!, {s29}
|
||||
fstmfdseq r4!, {s28}
|
||||
|
||||
fstmiaxeq r5, {d7}
|
||||
fstmeaxeq r6, {d8}
|
||||
itttt eq
|
||||
fstmiaxeq r7!, {d9}
|
||||
fstmeaxeq r8!, {d10}
|
||||
fstmdbxeq r9!, {d11}
|
||||
fstmfdxeq r10!, {d12}
|
||||
|
||||
@ Conversion operations
|
||||
|
||||
itttt eq
|
||||
fsitoseq s27, s6
|
||||
ftosiseq s25, s5
|
||||
ftosizseq s23, s4
|
||||
ftouiseq s21, s3
|
||||
itttt eq
|
||||
ftouizseq s19, s2
|
||||
fuitoseq s17, s1
|
||||
|
||||
@ ARM from VFP operations
|
||||
|
||||
fmrseq r11, s3
|
||||
fmrxeq r9, fpsid
|
||||
|
||||
@ VFP From ARM operations
|
||||
|
||||
itt eq
|
||||
fmsreq s3, r9
|
||||
fmxreq fpsid, r8
|
||||
|
||||
@ 2 nops to pad to 16-byte boundary
|
||||
nop
|
||||
nop
|
||||
17
gas/testsuite/gas/arm/vfp2_t2.d
Normal file
17
gas/testsuite/gas/arm/vfp2_t2.d
Normal file
@ -0,0 +1,17 @@
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: Thumb-2 VFP Additional instructions
|
||||
#as: -mfpu=vfp
|
||||
|
||||
# Test the ARM VFP Double Precision instructions
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+000 <[^>]*> ec4a 5b10 fmdrr d0, r5, sl
|
||||
0+004 <[^>]*> ec5a 5b10 fmrrd r5, sl, d0
|
||||
0+008 <[^>]*> ec4a 5a37 fmsrr r5, sl, {s15, s16}
|
||||
0+00c <[^>]*> ec5a 5a37 fmrrs r5, sl, {s15, s16}
|
||||
0+010 <[^>]*> ec45 ab1f fmdrr d15, sl, r5
|
||||
0+014 <[^>]*> ec55 ab1f fmrrd sl, r5, d15
|
||||
0+018 <[^>]*> ec45 aa38 fmsrr sl, r5, {s17, s18}
|
||||
0+01c <[^>]*> ec55 aa38 fmrrs sl, r5, {s17, s18}
|
||||
21
gas/testsuite/gas/arm/vfp2_t2.s
Normal file
21
gas/testsuite/gas/arm/vfp2_t2.s
Normal file
@ -0,0 +1,21 @@
|
||||
@ VFP2 Additional instructions
|
||||
@ Same as vfp2.s, but for Thumb-2
|
||||
.syntax unified
|
||||
.thumb
|
||||
.text
|
||||
.global F
|
||||
F:
|
||||
@ First we test the basic syntax and bit patterns of the opcodes.
|
||||
@ Use a combination of r5, r10, s15, s17, d0 and d15 to exercise
|
||||
@ the full register bitpatterns
|
||||
|
||||
fmdrr d0, r5, r10
|
||||
fmrrd r5, r10, d0
|
||||
fmsrr {s15, s16}, r5, r10
|
||||
fmrrs r5, r10, {s15, s16}
|
||||
|
||||
fmdrr d15, r10, r5
|
||||
fmrrd r10, r5, d15
|
||||
fmsrr {s17, s18}, r10, r5
|
||||
fmrrs r10, r5, {s17, s18}
|
||||
|
||||
@ -1,3 +1,12 @@
|
||||
2005-09-02 Paul Brook <paul@codesourcery.com>
|
||||
|
||||
* arm-dis.c (coprocessor_opcodes): New.
|
||||
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
|
||||
(print_insn_coprocessor): New function.
|
||||
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
|
||||
format characters.
|
||||
(print_insn_thumb32): Use print_insn_coprocessor.
|
||||
|
||||
2005-08-30 Paul Brook <paul@codesourcery.com>
|
||||
|
||||
* arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
|
||||
|
||||
1273
opcodes/arm-dis.c
1273
opcodes/arm-dis.c
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user