Yao Qi 3539aa13fb [ARM] Clear reserved bits in CPSR
Bits 20 ~ 23 of CPSR are reserved (RAZ, read as zero), but they are not
zero if the arm program runs on aarch64-linux.  AArch64 tracer gets PSTATE
from arm 32-bit tracee as CPSR, but bits 20 ~ 23 are used in PSTATE.  I
think kernel should clear these bits when it is read through ptrace, but
the fix in user space is still needed.

This patch fixes these two fails,

-FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr	d7, [r11, #-12]
-FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr	d7, [r7]

gdb:

2016-04-22  Yao Qi  <yao.qi@linaro.org>

	* aarch32-linux-nat.c (aarch32_gp_regcache_supply): Clear CPSR
	bits 20 to 23.

gdb/gdbserver:

2016-04-22  Yao Qi  <yao.qi@linaro.org>

	* linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20
	to 23.
2016-04-22 15:54:43 +01:00
2016-02-10 10:54:29 +00:00
2016-03-03 12:55:30 +10:30
2016-04-22 15:54:43 +01:00
2015-08-31 12:53:36 +09:30
2016-01-28 21:44:42 +01:00
2016-04-19 09:26:16 +01:00
2014-11-16 13:43:48 +01:00
2015-07-27 07:49:05 -07:00
2014-11-16 13:43:48 +01:00
2014-11-16 13:43:48 +01:00
2016-01-12 08:44:52 -08:00
2014-02-06 11:01:57 +01:00
2016-04-19 09:26:16 +01:00
2016-04-19 09:26:16 +01:00
2014-11-16 13:43:48 +01:00
2014-11-16 13:43:48 +01:00
2014-11-16 13:43:48 +01:00

		   README for GNU development tools

This directory contains various GNU compilers, assemblers, linkers, 
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