178 Commits

Author SHA1 Message Date
7f6ebecd56 bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]
Regenerating BPF target using the maintainer mode emits:
.../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow]
  57 |   64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }

The use of a narrow size to handle the mask CGEN in instruction format
is causing this error.  Additionally eBPF `call' instructions
constructed by expressions using symbols (BPF_PSEUDO_CALL) emits
annotations in `src' field of the instruction, used to identify BPF
target endianness.

cpu/
	* bpf.cpu (define-call-insn): Remove `src' field from
	instruction mask.

include/
	*opcode/cge.h (CGEN_IFMT): Adjust mask bit width.

opcodes/
	* bpf-opc.c: Regenerate.
2023-02-03 11:18:50 -06:00
a72b07181d Add markers for 2.40 branch 2022-12-31 12:05:28 +00:00
0bd0932314 Add markers for 2.39 branch 2022-07-08 10:41:07 +01:00
ddd7bf3e28 drop XC16x bits
Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved
the architecture from the "obsolete but still available" to the
"obsolete / support removed" list in config.bfd, making the architecture
impossible to enable (except maybe via "enable everything" options").

Note that I didn't touch */po/*.po{,t} on the assumption that these
would be updated by some (half)automatic means.
2022-06-27 11:11:46 +02:00
0dfdb5234a opcodes cgen: remove use of PTR
Note that opcodes is regenerated with cgen commit d1dd5fcc38e reverted,
due to failure of bpf to compile with that patch applied.

.../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow]
   57 |   64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
plus other similar errors.

cpu/
	* mep.opc (print_tpreg, print_spreg): Delete unnecessary
	forward declarations.  Replace PTR with void *.
	* mt.opc (print_dollarhex, print_pcrel): Delete forward decls.
opcodes/
	* bpf-desc.c, * bpf-dis.c, * cris-desc.c,
	* epiphany-desc.c, * epiphany-dis.c,
	* fr30-desc.c, * fr30-dis.c, * frv-desc.c, * frv-dis.c,
	* ip2k-desc.c, * ip2k-dis.c, * iq2000-desc.c, * iq2000-dis.c,
	* lm32-desc.c, * lm32-dis.c, * m32c-desc.c, * m32c-dis.c,
	* m32r-desc.c, * m32r-dis.c, * mep-desc.c, * mep-dis.c,
	* mt-desc.c, * mt-dis.c, * or1k-desc.c, * or1k-dis.c,
	* xc16x-desc.c, * xc16x-dis.c,
	* xstormy16-desc.c, * xstormy16-dis.c: Regenerate.
2022-05-11 09:49:20 +09:30
16089f320a opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblers
Currently, the get_disassembler() implementations for riscv, csky, and
rl78--and mep_print_insn() for mep--access ELF variants of union fields
without first checking that the bfd actually represents an ELF.  This
causes undefined behavior and crashes when disassembling non-ELF files
(the "binary" BFD, for example).  Fix that.
2022-04-30 19:21:11 +09:30
a74e1cb344 Add markers for 2.38 branch 2022-01-22 12:08:55 +00:00
4dcdbbd1bc Re: opcodes: constify & local meps macros
Commit f375d32b35ce changed a generated file.  Edit the source instead.

	* mep.opc (macros): Make static and const.
	(lookup_macro): Return and use const pointer.
	(expand_macro): Make mac param const.
	(expand_string): Make pmacro const.
2021-07-05 21:40:49 +09:30
514192487e Add markers for 2.37 branch 2021-07-03 14:50:57 +01:00
0b3e14c902 or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()
The gotha() relocation mnemonic will be outputted by OpenRISC GCC when
using the -mcmodel=large option.  This relocation is used along with
got() to generate 32-bit GOT offsets.  This increases the previous GOT
offset limit from the previous 16-bit (64K) limit.

This is needed on large binaries where the GOT grows larger than 64k.

bfd/ChangeLog:

	PR 21464
	* bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation.
	* elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise.
	(or1k_final_link_relocate, or1k_elf_relocate_section,
	or1k_elf_check_relocs): Likewise.
	* libbfd.h (bfd_reloc_code_real_names): Likewise.
	* reloc.c: Likewise.

cpu/ChangeLog:

	PR 21464
	* or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic
	for gotha() relocation.

include/ChangeLog:

	PR 21464
	* elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number.

opcodes/ChangeLog:

	PR 21464
	* or1k-asm.c: Regenerate.

gas/ChangeLog:

	PR 21464
	* testsuite/gas/or1k/reloc-1.s: Add test for new relocation.
	* testsuite/gas/or1k/reloc-1.d: Add test result for new
	relocation.

Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>

fixup reloc, add tests
2021-05-06 20:51:24 +09:00
78933a4ad9 Use bool in opcodes
cpu/
	* frv.opc: Replace bfd_boolean with bool, FALSE with false, and
	TRUE with true throughout.
opcodes/
	* sysdep.h (POISON_BFD_BOOLEAN): Define.
	* aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
	* aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
	* aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
	* arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
	* cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
	* disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
	* i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
	* microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
	* mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
	* msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
	* ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
	* tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
	* xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
	and TRUE with true throughout.
2021-03-31 10:49:23 +10:30
3d7d6c1b50 opcodes int vs bfd_boolean fixes
cpu/
	* frv.opc (frv_is_branch_major, frv_is_float_major),
	(frv_is_media_major, frv_is_branch_insn, frv_is_float_insn),
	(frv_is_media_insn, spr_valid): Correct prototypes.
include/
	* opcode/aarch64.h (aarch64_opcode_encode): Correct prototype.
opcodes/
	* arc-dis.c (extract_operand_value): Correct NULL cast.
	* frv-opc.h: Regenerate.
2021-03-29 11:22:21 +10:30
055bc77a80 Add Changelog entries and NEWS entries for 2.36 branch 2021-01-09 10:40:28 +00:00
0cc79db2b6 Fix spelling mistakes 2020-10-05 14:20:15 +01:00
6e25f88828 bpf: xBPF SDIV, SMOD instructions
Add gas and opcodes support for two xBPF-exclusive ALU operations:
SDIV (signed division) and SMOD (signed modulo), and add tests for
them in gas.

cpu/
	* bpf.cpu (insn-op-code-alu): Add SDIV and SMOD.
	(define-alu-insn-bin, daib): Take ISAs as an argument.
	(define-alu-instructions): Update calls to daib pmacro with
	ISAs; add sdiv and smod.

gas/
	* testsuite/gas/bpf/alu-xbpf.d: New file.
	* testsuite/gas/bpf/alu-xbpf.s: Likewise.
	* testsuite/gas/bpf/alu32-xbpf.d: Likewise.
	* testsuite/gas/bpf/alu32-xbpf.d: Likewise.
	* testuiste/gas/bpf/bpf.exp: Run new tests.

opcodes/
	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-opc.h: Likewise.
2020-09-18 10:04:23 -07:00
3ad6c19423 bpf: simulator: correct div, mod insn semantics
The div and mod eBPF instructions are unsigned, but the semantic
specification for the simulator incorrectly used signed operators.
Correct them to unsigned versions, and correct the ALU tests in
the simulator (which incorrectly assumed signed semantics).

Tested in bpf-unknown-none.

cpu/ChangeLog:
2020-09-08  David Faust  <david.faust@oracle.com>

	* bpf.cpu (define-alu-instructions): Correct semantic operators
	for div, mod to unsigned versions.

sim/ChangeLog:
2020-09-08  David Faust  <david.faust@oracle.com>

	* bpf/sem-be.c: Regenerate.
	* bpf/sem-le.c: Likewise.

sim/testsuite/ChangeLog:
2020-09-08  David Faust  <david.faust@oracle.com>

	* sim/bpf/alu.s: Correct div and mod tests.
	* sim/bpf/alu32.s: Likewise.
2020-09-08 11:39:07 -07:00
8dbe96f070 mep: ubsan: mep-ibld.c:1635,1645,1652 left shift of negative value
cpu/
	* mep-core.cpu (f-8s8a2, f-12s4a2, f-17s16a2): Multiply signed
	value by two rather than shifting left.
	(f-24s5a2n): Similarly multiply signed f-24s5a2n-hi to extract.
opcodes/
	* mep-ibld.c: Regenerate.
2020-09-01 16:03:08 +09:30
4449c81a85 bpf: add xBPF ISA
This patch adds support for xBPF, another ISA targetting the BPF
virtual architecture. For now, the primary difference between eBPF
and xBPF is that xBPF supports indirect calls through the
'call %reg' form of the call instruction.

bfd/
	* archures.c (bfd_mach_xbpf): Define.
	* bfd-in2.h: Regenerate.
	* cpu-bpf.c (bfd_xbpf_arch) New.
	(bfd_bpf_arch) Update next in list field to point to xbpf arch.

cpu/
	* bpf.cpu (arch bpf): Add xbpf mach and isas.
	(define-xbpf-isa) New pmacro.
	(all-isas) Add xbpfle,xbpfbe.
	(endian-isas): New pmacro.
	(mach xbpf): New.
	(model xbpf-def): Likewise.
	(h-gpr): Add xbpf mach.
	(f-dstle, f-srcle, dstle, srcle): Add xbpfle isa.
	(f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa.
	(define-alu-insn-un): Use new endian-isas pmacro.
	(define-alu-insn-bin, define-alu-insn-mov): Likewise.
	(define-endian-insn, define-lddw): Likewise.
	(dlind, dxli, dxsi, dsti): Likewise.
	(define-cond-jump-insn, define-call-insn): Likewise.
	(define-atomic-insns): Likewise.

gas/
	* config/tc-bpf.c: Add option -mxbpf to select xbpf isa.
	* testsuite/gas/bpf/indcall-1.d: New file.
	* testsuite/gas/bpf/indcall-1.s: Likewise.
	* testsuite/gas/bpf/indcall-bad-1.l: Likewise.
	* testsuite/gas/bpf/indcall-bad-1.s: Likewise.
	* testsuite/gas/bpf/bpf.exp: Run new tests.

opcodes/
	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-opc.h: Likewise.
	* disassemble.c (disassemble_init_for_target): Set bits for xBPF
	ISA when appropriate.
2020-08-26 15:39:00 +02:00
b115b9fd3c Add markers for binutils 2.35 branch 2020-07-04 10:16:22 +01:00
d73be61168 cpu: fix offset16 type, update c-calls in bpf.cpu
Correct the type of the offset16 field to HI, and simplify memory
accesses which use it. Also update c-calls in semantics for a
few instructions.

cpu/ChangeLog:

2020-06-25 David Faust  <david.faust@oracle.com>

	* bpf.cpu (f-offset16): Change type from INT to HI.
	(dxli): Simplify memory access.
	(dxsi): Likewise.
	(define-endian-insn): Update c-call in semantics.
	(dlabs) Likewise.
	(dlind) Likewise.
2020-06-25 20:34:29 +02:00
d8740be159 cpu,gas,opcodes: remove no longer needed workaround from the BPF port
cpu/ChangeLog:

2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
	* bpf.opc (bpf_print_insn): Do not set endian_code here.

gas/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
	bpf_cgen_cpu_open.
	(md_assemble): Remove no longer needed hack.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* disassemble.c (disassemble_init_for_target): Set endian_code for
	bpf targets.
	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.
2020-06-04 16:17:42 +02:00
e9bffec9af opcodes: discriminate endianness and insn-endianness in CGEN ports
The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value.  These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.

The process of writing an instruction to the object file is:

  a) cgen_put_insn_value        ;; Writes out the opcodes.
  b) ARCH_cgen_insert_operand
       insert_normal
         insert_1
           cgen_put_insn_value  ;; Writes out the bytes of the
                                ;; operand.

Likewise, the process of reading an instruction from the object file
is:

  a) cgen_get_insn_value        ;; Reads the opcodes.
  b) ARCH_cgen_extract_operand
       extract_normal
         extract_1
           cgen_get_insn_value  ;; Reads in the bytes of the
                                ;; operand.

As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.

This is problematic for architectures in which the endianness of
instructions is different to the endianness of data.  An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.

This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate.  Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.

A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value.  It has been adapted to
  pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
  It has been adapted to pass the new endianargument.  Ditto for a
  call in the assembler.

Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.

include/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/cgen.h: Get an `endian' argument in both
	cgen_get_insn_value and cgen_put_insn_value.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
	(cgen_put_insn_value): Likewise.
	(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
	* cgen-dis.in (print_insn): Likewise.
	* cgen-ibld.in (insert_1): Likewise.
	(insert_1): Likewise.
	(insert_insn_normal): Likewise.
	(extract_1): Likewise.
	* bpf-dis.c: Regenerate.
	* bpf-ibld.c: Likewise.
	* bpf-ibld.c: Likewise.
	* cgen-dis.in: Likewise.
	* cgen-ibld.in: Likewise.
	* cgen-opc.c: Likewise.
	* epiphany-dis.c: Likewise.
	* epiphany-ibld.c: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-ibld.c: Likewise.
	* frv-dis.c: Likewise.
	* frv-ibld.c: Likewise.
	* ip2k-dis.c: Likewise.
	* ip2k-ibld.c: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-ibld.c: Likewise.
	* lm32-dis.c: Likewise.
	* lm32-ibld.c: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-ibld.c: Likewise.
	* mep-dis.c: Likewise.
	* mep-ibld.c: Likewise.
	* mt-dis.c: Likewise.
	* mt-ibld.c: Likewise.
	* or1k-dis.c: Likewise.
	* or1k-ibld.c: Likewise.
	* xc16x-dis.c: Likewise.
	* xc16x-ibld.c: Likewise.
	* xstormy16-dis.c: Likewise.
	* xstormy16-ibld.c: Likewise.

gas/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen.c (gas_cgen_finish_insn): Pass the endianness to
	cgen_put_insn_value.
	(gas_cgen_md_apply_fix): Likewise.
	(gas_cgen_md_apply_fix): Likewise.
	* config/tc-bpf.c (md_apply_fix): Pass data endianness to
	cgen_put_insn_value.
	* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
	cgen_put_insn_value.

cpu/ChangeLog:

2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* mep.opc (print_slot_insn): Pass the insn endianness to
	cgen_get_insn_value.
2020-06-04 16:17:42 +02:00
78c1c35437 cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes
This patch adds semantic RTL descriptions to the eBPF instructions
defined in cpu/bpf.cpu.  It also contains a couple of minor
improvements.

Tested in bpf-unknown-none targets.
No regressions.

cpu/ChangeLog:

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf.cpu (define-alu-insn-un): Add definitions of semantics.
	(define-alu-insn-mov): Likewise.
	(daib): Likewise.
	(define-alu-instructions): Likewise.
	(define-endian-insn): Likewise.
	(define-lddw): Likewise.
	(dlabs): Likewise.
	(dlind): Likewise.
	(dxli): Likewise.
	(dxsi): Likewise.
	(dsti): Likewise.
	(define-ldstx-insns): Likewise.
	(define-st-insns): Likewise.
	(define-cond-jump-insn): Likewise.
	(dcji): Likewise.
	(define-condjump-insns): Likewise.
	(define-call-insn): Likewise.
	(ja): Likewise.
	("exit"): Likewise.
	(define-atomic-insns): Likewise.
	(sem-exchange-and-add): New macro.
	* bpf.cpu ("brkpt"): New instruction.
	(bpfbf): Set word-bitsize to 32 and insn-endian big.
	(h-gpr): Prefer r0 to `a' and r6 to `ctx'.
	(h-pc): Expand definition.
	* bpf.opc (bpf_print_insn): Set endian_code to BIG.

opcodes/ChangeLog:

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.
2020-05-28 21:52:31 +02:00
d96bf37ba8 Replace "if (x) free (x)" with "free (x)", opcodes
cpu/
	* mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace
	"if (x) free (x)" with "free (x)".
opcodes/
	* arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
	* sparc-dis.c: Likewise.
	* tic4x-dis.c: Likewise.
	* xtensa-dis.c: Likewise.
	* bpf-desc.c: Regenerate.
	* epiphany-desc.c: Regenerate.
	* fr30-desc.c: Regenerate.
	* frv-desc.c: Regenerate.
	* ip2k-desc.c: Regenerate.
	* iq2000-desc.c: Regenerate.
	* lm32-desc.c: Regenerate.
	* m32c-desc.c: Regenerate.
	* m32r-desc.c: Regenerate.
	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mt-desc.c: Regenerate.
	* or1k-desc.c: Regenerate.
	* xc16x-desc.c: Regenerate.
	* xstormy16-desc.c: Regenerate.
2020-05-21 10:45:33 +09:30
ae440402f5 or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts
Reported by Rich Felker when building on 32-bit hosts.  Backwards jump
negative offsets were not calculated correctly due to improper 32-bit
to 64-bit zero-extension.  The 64-bit fields are present because we
are mixing 32-bit and 64-bit architectures in our cpu descriptions.

Removing 64-bit fixes the issue.  We don't use 64-bit, there is an architecture
spec for 64-bit but no implementations or simulators.  My thought is if
we need them in the future we should do the proper work to support both
32-bit and 64-bit implementations co-existing then.

cpu/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	PR 25184
	* or1k.cpu (arch or1k): Remove or64 and or64nd machs.
	(ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
	(cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
	* or1kcommon.cpu (h-fdr): Remove hardware.
	* or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
	(float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
	(float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
	(float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
	(lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
2020-05-19 20:40:27 +09:00
c54a9b5669 cpu,gas,opcodes: support for eBPF JMP32 instruction class
Add support for the JMP32 class of eBPF instructions.

cpu/ChangeLog

	* bpf.cpu (define-cond-jump-insn): Renamed from djci.
	(dcji) New version with support for JMP32

gas/ChangeLog

	* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
	* testsuite/gas/bpf/jump32.s: New file.
	* testsuite/gas/bpf/jump32.d: Likewise.

opcodes/ChangeLog

	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Regenerate.
	* bpf-opc.h: Likewise.
2020-04-16 09:52:57 +02:00
44e4546fa2 ubsan: m32c: left shift of negative value
cpu/
	* m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-02-03 15:59:08 +10:30
b2b1453ad4 ubsan: frv: left shift of negative value
More non-bugs flagged by ubsan, unless you happen to be compiling for
a 1's complement host.

cpu/
	* frv.cpu (f-u12): Multiply rather than left shift signed values.
	(f-label16, f-label24): Likewise.
opcodes/
	* frv-ibld.c: Regenerate.
2020-02-01 23:23:18 +10:30
0c115f8483 ubsan: m32c: left shift of negative value
More nonsense fixing "bugs" with left shifts of signed values.  Yes,
the C standard does say this is undefined (and right shifts of signed
values are implementation defined BTW) but in practice there is no
problem with current machines.  1's complement is a thing of the past.

cpu/
	* m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
	(f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise.
	(f-dst32-rn-prefixed-QI): Likewise.
	(f-dsp-32-s32): Mask before shifting left.
	(f-dsp-48-u32, f-dsp-48-s32): Likewise.
	(f-bitbase32-16-s11-unprefixed): Multiply signed field rather than
	shifting left.
	(f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise.
	(h-gr-SI): Mask before shifting.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-01-30 23:39:55 +10:30
bd434cc4d9 cpu,opcodes,gas: fix neg and neg32 instructions in BPF
This patch fixes the neg/neg32 BPF instructions, which have K (=0)
instead of X (=1) in their header source bit, despite operating on
registes.

cpu/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (define-alu-insn-un): The unary BPF instructions
	(neg and neg32) use OP_SRC_K even if they operate only in
	registers.

opcodes/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c: Regenerate.

gas/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Update expected opcode for `neg'.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise for `neg32'.
	* testsuite/gas/bpf/alu32-be.d: Likewise.
2020-01-30 13:59:04 +01:00
ae77468624 Add markers for 2.34 branch to the NEWS files and ChangeLogs. 2020-01-18 13:50:25 +00:00
202e762b32 ubsan: fr30: left shift of negative value
cpu/
	* fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't
	left shift signed values.
opcodes/
	* fr30-ibld.c: Regenerate.
2020-01-13 12:12:05 +10:30
cc6aa1a6e0 ubsan: m32c: left shift of negative value
There are probably a lot more of these still here.

cpu/
	* m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign
	bits before shifting rather than masking after shifting.
	(f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise.
	(f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise.
	(f-dsp-64-u16, f-dsp-8-s24): Likewise.
	(f-bitbase32-16-s19-unprefixed): Avoid signed left shift.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-01-06 21:53:51 +10:30
c9ae58fe32 ubsan: m32r: left shift of negative value
cpu/
	* m32r.cpu (f-disp8): Avoid left shift of negative values.
	(f-disp16, f-disp24): Likewise.
opcodes/
	* m32r-ibld.c: Regenerate.
2020-01-04 19:20:33 +10:30
3e1056a1a6 ubsan: iq2000: left shift of negative value
cpu/
	* iq2000.cpu (f-offset): Avoid left shift of negative values.
opcodes/
	* iq2000-ibld.c: Regenerate.
2019-12-23 18:04:12 +10:30
bcd9f578a9 ubsan: or1k: left shift of negative value
cpu/
	* or1korbis.cpu (f-disp26, f-disp21): Don't left shift negative values.
opcodes/
	* or1k-ibld.c: Regenerate.
2019-12-20 17:57:58 +10:30
62e6599087 ubsan: bpf: left shift cannot be represented in type 'DI' (aka 'long')
cpu/
	* bpf.cpu (f-imm64): Avoid signed overflow.
opcodes/
	* bpf-ibld.c: Regenerate.
2019-12-17 14:32:23 +10:30
e6ced26afd ubsan: xstormy16: left shift of negative value
cpu/
	* xstormy16.cpu (f-rel12a): Avoid signed overflow.
opcodes/
	* xstormy16-ibld.c: Regenerate.
2019-12-16 17:35:13 +10:30
1d61b03226 Remove more shifts for sign/zero extension
cpu/
	* epiphany.cpu (f-sdisp11): Don't sign extend with shifts.
	* lm32.cpu (f-branch, f-vall): Likewise.
	* m32.cpu (f-lab-8-16): Likewise.
opcodes/
	* arc-dis.c (BITS): Don't truncate high bits with shifts.
	* nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
	* tic54x-dis.c (print_instruction): Likewise.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.
	* tilepro-opc.c (parse_insn_tilepro): Likewise.
	* visium-dis.c (disassem_class0): Likewise.
	* pdp11-dis.c (sign_extend): Likewise.
	(SIGN_BITS): Delete.
	* epiphany-ibld.c: Regenerate.
	* lm32-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
2019-12-11 21:14:19 +10:30
b8e61daa1a ubsan: epiphany: left shift of negative value
Two places in epiphany_cgen_extract_operand, "value" is a long.
        value = ((((value) << (1))) + (pc));

cpu/
	* epiphany.cpu (f-simm8, f-simm24): Use multiply rather than
	shift left to avoid UB on left shift of negative values.
opcodes/
	* epiphany-ibld.c: Regenerate.
2019-12-11 11:34:33 +10:30
e042e6c3e2 cpu: fix comment in bpf.cpu
2019-11-20  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu: Fix comment describing the 128-bit instruction format.
2019-11-20 10:16:24 +01:00
60391a255b Add markers for 2.33 branch to NEWS and ChangeLog files. 2019-09-09 10:27:40 +01:00
231097b03a cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler
This patch changes the eBPF CPU description to prefer the register
names %r0 and %r6 instead of %a and %ctx when disassembling.  This
matches better with the current practice, vs. cBPF.

It also updates the GAS tests in order to reflect this change.
Tested in a x86_64 host.

cpu/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
	%a and %ctx.

opcodes/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerated.

gas/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.
	* testsuite/gas/bpf/lddw-be.d: Likewise.
	* testsuite/gas/bpf/lddw.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise.
2019-07-19 15:35:43 +02:00
3719fd55b6 cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions
This patch fixes the eBPF CPU description in order to reflect the
right explicit arguments passed to the ldabs{b,h,w,dw} instructions,
updates the corresponding GAS tests, and updates the BPF section of
the GAS manual.

cpu/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (dlabs): New pmacro.
	(dlind): Likewise.

opcodes/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-opc.h: Likewise.

gas/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'
	register as an argument.
	* testsuite/gas/bpf/mem.d: Updated accordingly.
	* testsuite/gas/bpf/mem-be.d: Likewise.
	* doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct
	explicit arguments to ldabs and ldind instructions.
2019-07-15 16:00:28 +02:00
92434a14b9 cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions
The eBPF non-generic load instructions ldind{b,h,w,dw} and
ldabs{b,h,w,dw} do not take an explicit destination register as an
argument.  Instead, they put the loaded value in %r0, implicitly.

This patch fixes the CPU BPF description to not expect a 'dst'
argument in these arguments, regenerates the corresponding files in
opcodes, and updates the impacted GAS tests.

Tested in a x86-64 host.

cpu/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (dlsi): ldabs and ldind instructions do not take an
	explicit 'dst' argument.

opcodes/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.

gas/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: Do not use explicit arguments for
	ldabs and ldind instructions.
	* testsuite/gas/bpf/mem.d: Updated accordingly.
	* testsuite/gas/bpf/mem-be.d: Likewise.
2019-07-14 14:45:31 +02:00
a2e4218f23 cpu/or1k: Update fpu compare symbols to imply set flag
The fpu compare symbols where not including 'sf' in the mnemonic.  So
instead of `lf-sfeq` (implying set flag if operands are equal) we were
having `lf-eq`.   This patch adds the 'sf'.  This helps with making the
generated CGEN documentation consistent and ordered correctly.

cpu/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol.
2019-06-13 06:16:19 +09:00
eb212c84a1 cpu/or1k: Document no branch delay slot architectures and l.adrp
The 'nd' architectures did not mention what the 'nd' stands for.
Document that these mean 'no brach delay slot'.

cpu/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a
	(l-adrp): Improve comment.
2019-06-13 06:16:19 +09:00
d3ad6278d6 cpu/or1k: Define unordered comparisons
Add support for new floating point unordered comparisons.  These have been
defined in OpenRISC architecture proposal 7[0] and are now included in the
architecture specification 1.3.

These new instructions provide the ability for floating point comparisons to
detect NaNs.

[0] https://openrisc.io/proposals/lfsf

cpu/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S,
	SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D,
	SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes.
	(float-setflag-insn-base): New pmacro based on float-setflag-insn.
	(float-setflag-symantics, float-setflag-unordered-cmp-symantics,
	float-setflag-unordered-symantics): New pmacro for instruction
	symantics.
	(float-setflag-insn): Update to use float-setflag-insn-base.
	(float-setflag-unordered-insn): New pmacro for generating instructions.
2019-06-13 06:16:19 +09:00
6ce26ac7c3 cpu/or1k: Add support for orfp64a32 spec
This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by
using register pairs.  The functionality has been added to OpenRISC architecture
specification version 1.3 as per architecture proposal 14[0].

For supporting assembly of both 64-bit and 32-bit precision instructions we have
defined CGEN_VALIDATE_INSN_SUPPORTED.  This allows cgen to use 64-bit bit
architecture assembly parsing on 64-bit toolchains and 32-bit architecture
assembly parsing on 32-bit toolchains.  Without this the assembler has issues
parsing register pairs.

This patch also contains a few fixes to the symantics for existing OpenRISC
single and double precision FPU operations.

[0] https://openrisc.io/proposals/orfpx64a32

cpu/ChangeLog:

yyyy-mm-dd  Andrey Bacherov  <avbacherov@opencores.org>
	    Stafford Horne  <shorne@gmail.com>

	* or1k.cpu (ORFPX64A32-MACHS): New pmacro.
	(ORFPX-MACHS): Removed pmacro.
	* or1k.opc (or1k_cgen_insn_supported): New function.
	(CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
	(parse_regpair, print_regpair): New functions.
	* or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
	and add comments.
	(h-fdr): Update comment to indicate or64.
	(reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
	(h-fd32r): New hardware for 64-bit fpu registers.
	(h-i64r): New hardware for 64-bit int registers.
	* or1korbis.cpu (f-resv-8-1): New field.
	* or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
	(rDDF, rADF, rBDF): Update operand comment to indicate or64.
	(f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
	(h-roff1): New hardware.
	(double-field-and-ops mnemonic): New pmacro to generate operations
	rDD32F, rAD32F, rBD32F, rDDI and rADI.
	(float-regreg-insn): Update single precision generator to MACH
	ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
	(float-setflag-insn): Update single precision generator to MACH
	ORFPX32-MACHS.  Fix double instructions from single to double
	precision.  Add generator for or32 64-bit instructions.
	(float-cust-insn cust-num): Update single precision generator to MACH
	ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
	(lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
	ORFPX32-MACHS.
	(lf-rem-d): Fix operation from mod to rem.
	(lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
	(lf-itof-d): Fix operands from single to double.
	(lf-ftoi-d): Update operand mode from DI to WI.
2019-06-13 06:16:18 +09:00
ea195bb04c cpu: add eBPF cpu description
This patch adds a CPU description for the Linux kernel eBPF virtual
machine, plus supporting code for disassembler and assembler.

cpu/ChangeLog:

2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu: New file.
	* bpf.opc: Likewise.
2019-05-23 19:33:50 +02:00