All funcs already call other funcs that don't return. The mips port is
the only exception because its generic exception handler can return in
the case of normal exceptions. So while the exceptions its signal handler
triggers doesn't return, we can't express that conditional logic. So add
some useless abort calls to make the compiler happy.
The compiler pointed out that we're testing LAST_TIMER_REG and
LAST_COUNTER which are the same value ... and that's because we
set LAST_TIMER_REG to the wrong register. Fix the typo.
The compiler pointed out we checked AZ twice. Sort by name to avoid
that in the future, and to make it clearer that we have coverage of
all the bits. And add the bits we were missing.
The order here doesn't matter as it's just turning a pointer into a
human readable string when store tracing is enabled.
The scache vars aren't used by ports in the pbb & fast codepaths,
nor are they documented as inputs to the callbacks, so delete them
to avoid unused variable compiler warnings.
Pull out the common parts of the genmloop invocation into the common
code. This will make it easier to add more, and make the per-port
differences a little more obvious.
Fix one minor pointer-sign warning to enable warnings in general
for this file. Reading the data as signed and then returning it
as unsigned should be functionally the same in this case.
This came up testing the CRC optimization work from Mariam@RAU.
Basically to optimize some CRC loops into table lookups or carryless
multiplies, we may need to do a bit reflection, which on the mcore
processor is done using a rotate instruction.
Unfortunately the simulator implementation of rotates has the exact same
problem as we saw with right shifts. The input value may have been sign
extended from 32 to 64 bits. When we rotate the extended value, we get
those sign extension bits and thus the wrong result.
The fix is the same. Rather than using a "long", use a uint32_t for the
type of the temporary. This fixes a handful of tests in the GCC testsuite:
The push/pop insns only have 2 operands, so delete unused "c".
The pushret/popret insns use 2 operands, but they don't implement the
logic directly, they call the push/pop implementations. So delete the
unused "a" & "b".
The pmuls encoding is incorrect -- it looks like a copy & paste error
from the padd pmuls variant. The SuperH software manual covers this.
On the flip side, the manual lists pwsb & pwad as insns that exist,
but no description of what they do, what the insn name means, or the
actual encoding. Our sim implementation stubs them both out as nops.
Let's mark the fields to avoid unused variable warnings.
Fix a few problems caught by compiler warnings:
* Some of the asr & lsr insns were setting up the c state flag,
but then forgetting to set it in the PSW. Add it like the other
asr & lsr variants.
* Some of the dmulh insns were multiplying one of the source regs
against itself instead of against the other source reg.
* The sat16_cmp parallel insn was using the wrong register in the
compare -- the reg1 src/dst pair are used in the sat16 op, and
the reg2 src/dst pair are used in the add op.
The migration to local.mk in commit 0a129eb19a
accidentally listed the deps for all mloop steps as mloop.in instead of the
various variants that m32r uses.
Reported-by: Simon Marchi <simon.marchi@polymtl.ca>
The mloop.in code does this, but these variants do not. Use it to
avoid unused function warnings. The fast_p logic in these files
also looks off, but that'll require a bit more work to fixup.
CC m32r/mloopx.o
m32r/mloopx.c:37:1: error: ‘m32rxf_fill_argbuf_tp’ defined but not used [-Werror=unused-function]
37 | m32rxf_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
| ^~~~~~~~~~~~~~~~~~~~~
CC m32r/mloop2.o
m32r/mloop2.c:37:1: error: ‘m32r2f_fill_argbuf_tp’ defined but not used [-Werror=unused-function]
37 | m32r2f_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
| ^~~~~~~~~~~~~~~~~~~~~
Reported-by: Simon Marchi <simon.marchi@polymtl.ca>
Tested-By: Simon Marchi <simon.marchi@polymtl.ca>
