89121 Commits

Author SHA1 Message Date
1d65abb5e2 Formatting changes for RISC-V
This is a mixed bag of format changes:

 * Replacing constants with macros (0xffffffff with MINUS_ONE, for
   example).  There's one technically functional change in here (some
   MINUS_ONEs are changed to 0), but it only changes the behavior of an
   otherwise-unused field.
 * Using 0 instead of 0x0 in the relocation table.
 * There were some missing spaces before parens, the spaces have been
   added.
 * A handful of comments are now more descriptive.
 * A bunch of whitespace-only changes, mostly alignment and brace
   newlines.

bfd/
	* elfnn-riscv.c: Formatting and comment fixes throughout.
	* elfxx-riscv.c: Likewise.
	(howto_table): Change the src_mask field from MINUS_ONE to 0 for
	R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32,
	R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64.
opcodes/
	* riscv-opc.c: Formatting fixes.
gas/
	* config/tc-riscv.c: Formatting and comment fixes throughout.
2016-12-20 12:26:33 +10:30
96b0927de3 Improve RISC-V LD error message
I recently ran into this error message and found it's not helpful: it
just tells me some temporary file can't be linked.  This slightly
improved one at least tells me it's because of an elf32/elf64 conflict.

	* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Improve
	error message when linking elf32 and elf64.
2016-12-20 12:26:22 +10:30
dd1d944e23 Add opcodes RISC-V dependencies
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
	* Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
2016-12-20 12:26:08 +10:30
412ffd830b Fix problem where linker does not place .note sections according to script.
gold/
	PR gold/14676
	PR gold/20983
	* layout.h (Layout::choose_output_section): Add match_input_spec
	parameter. Adjust all callers.
	* layout.cc (Layout::choose_output_section): Likewise.  Pass
	match_input_spec to Script_sections::output_section_name().
	(Layout::create_note): Pass true for match_input_spec.
	* script-sections.h (Script_sections::output_section_name): Add
	match_input_spec parameter.
	* script-sections.cc (Sections_element::output_section_name): Likewise.
	(Output_section_definition::output_section_name): Likewise.
	(Script_sections::output_section_name): Likewise.
2016-12-19 17:22:10 -08:00
ec5882fbd1 Automatic date update in version.in 2016-12-20 00:00:32 +00:00
ee7ef219cb Fix an internal error in the constructor of Target_arm.
gold/
	* arm.cc (Target_arm::Target_arm): Move initialization code ...
	(Target_arm::do_select_as_default_target): ... to here.
	* testsuite/Makefile.am (arm_target_lazy_init): New test case.
	* testsuite/Makefile.in: Regenerate.
	* testsuite/arm_target_lazy_init.s: New source file.
	* testsuite/arm_target_lazy_init.t: New linker script.
2016-12-19 15:28:28 -08:00
89ede9f53b Fix forced allocation of common (-d) during -r links.
If the .bss section has other data in it besides common allocations,
gold was subtracting the wrong section start address from the symbol
value.

gold/
	PR gold/20976
	* symtab.cc (Symbol_table::sized_write_globals): Use address of
	output section, not input section.
	* testsuite/Makefile.am (pr20976): New test case.
	* testsuite/Makefile.in: Regenerate.
	* testsuite/pr20976.c: New source file.
2016-12-19 10:37:34 -08:00
16e69324ec Clean up gdb.gdb/selftest.exp
I recently see the test fails like this,

(gdb) PASS: gdb.gdb/selftest.exp: step over argv initialization
list^M
487       std::vector<struct cmdarg> cmdarg_vec;^M
(gdb) FAIL: gdb.gdb/selftest.exp: unknown source line (after step over argv initialization)

step^M
std::vector<cmdarg, std::allocator<cmdarg> >::vector (this=0x7fffffffdc10) at ../../binutils-gdb/gdb/main.c:487^M
487       std::vector<struct cmdarg> cmdarg_vec;^M
(gdb) FAIL: gdb.gdb/selftest.exp: step into xmalloc call

These fails are caused by using std::vector in commit
f60ee22ea1d62f7004511ec65a3ad76890032d88.  selttest.exp should match
the source code of GDB.  It is a maintenance pain, so this patch
removes do_steps_and_nexts.

gdb/testsuite:

2016-12-19  Yao Qi  <yao.qi@linaro.org>

	* gdb.gdb/selftest.exp (do_steps_and_nexts): Remove.
	(test_with_self): Don't call do_steps_and_nexts, and remove
	code about stepping into xmalloc.
2016-12-19 15:00:32 +00:00
b25e998d0b bfd/elf32-arm.c: Rename 'popcount' to 'elf32_arm_popcount'
bfd/elf32_arm.c contains a function 'popcount' which conflicts
with a function of the same name in NetBSD's libc.
This change also changes popcount's 'sum' variable to signed
since the function returns a signed integer.

bfd/
* elf32-arm.c (elf32_arm_popcount): Rename from 'popcount'.  Make
'sum' local variable signed.
2016-12-19 14:03:26 +01:00
91068ec6ae MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLE
Correct commit 640c0ccdc980 ("some objdump -M options, better reg
dumps"), <https://sourceware.org/ml/binutils/2002-12/msg00706.html>, and
only execute code setting up disassembler options based on ELF file
structures if SYMTAB_AVAILABLE is set.

	opcodes/
	* mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
	Only examine ELF file structures here.
2016-12-19 11:39:20 +00:00
4df995c771 MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64
Complement commit 5e7fc731f80e ("MIPS/opcodes: Also set disassembler's
ASE flags from ELF structures") and fix an `--enable-targets=all' GDB
build regression on 32-bit hosts where the MIPS target is a secondary:

../opcodes/libopcodes.a(mips-dis.o): In function `set_default_mips_dis_options':
mips-dis.c:(.text+0x906): undefined reference to `bfd_mips_elf_get_abiflags'
collect2: error: ld returned 1 exit status
make[2]: *** [gdb] Error 1

by avoiding making a call to the `bfd_mips_elf_get_abiflags' function,
which is not available, because there is no MIPS/ELF BFD included in
32-bit BFD builds.  This call is only made from a conditional code block
guarded by a check against `bfd_target_elf_flavour', which is dead in
such a configuration, however cannot be optimized away by the compiler.
Also some other MIPS BFDs may be available, such as a.out, ECOFF or PE,
so the disassembler has to remain functional.

	opcodes/
	* mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
	`bfd_mips_elf_get_abiflags' here.
2016-12-19 11:37:58 +00:00
602a81860a Automatic date update in version.in 2016-12-19 00:00:21 +00:00
53eab0d3fa Automatic date update in version.in 2016-12-18 00:00:24 +00:00
ddb9ad345c Automatic date update in version.in 2016-12-17 00:00:25 +00:00
97f00e367c Darwin: Fix gdb compilation.
Due to changes introduced by
commit 4d01a485d29732b19743e8b138897f3509e071b0
('struct expression *' -> gdb::unique_xmalloc_ptr<expression>)
compilation is broken on Darwin.

../gdb/darwin-nat-info.c:733:8: error: assigning to 'struct expression *'
from incompatible type
'expression_up' (aka 'std::__1::unique_ptr<expression, gdb::xfree_deleter<expression> >')
expr = parse_expression (exp);

Beside compilation, memory leak was solved as 'make_clean_up' was not called in previous
version.

2016-12-16  Bernhard Heckel  <bernhard.heckel@intel.com>

gdb/Changelog:
	* darwin-nat-info.c (info_mach_region_command): Use expression_up.
2016-12-16 13:39:52 +01:00
db7b55faa1 Fix compile time warning building arm-dis.c 2016-12-16 10:59:36 +00:00
221855059a Implement and document --gc-keep-exported
include/
	* bfdlink.h (struct bfd_link_info): Add gc_keep_exported.
bfd/
	* elflink.c (bfd_elf_gc_mark_dynamic_ref_symbol): Add handling
	for info->gc_keep_exported.
	(bfd_elf_gc_sections): Likewise.
ld/
	* ld.texinfo: Document --gc-keep-exported.
	* ldlex.h (enum option_values): Add OPTION_GC_KEEP_EXPORTED.
	* lexsup.c (parse_args): Add handling for --gc-keep-exported.
2016-12-16 13:49:03 +10:30
4c4067e410 Automatic date update in version.in 2016-12-16 00:00:26 +00:00
a961cdd5f1 Linking non-ELF file broken by PR20908 fix
PR ld/20968
	PR ld/20908
	* elflink.c (bfd_elf_final_link): Revert 2016-12-02 change.  Move
	reloc counting code later after ELF flavour test.
2016-12-15 23:53:49 +10:30
02aa377fbd Automatic date update in version.in 2016-12-15 00:00:24 +00:00
cadf97cf20 MAINTAINERS: Add myself as a MIPS maintainer
* MAINTAINERS (Maintainers for particular sims): Add myself as
	a MIPS maintainer.
2016-12-14 22:19:08 +00:00
5e7fc731f8 MIPS/opcodes: Also set disassembler's ASE flags from ELF structures
Respect any ASE flags recorded in ELF file structures for the purpose of
selecting instructions to be disassembled, preventing code from being
hex-dumped even though having been clearly indicated as valid at the
assembly time.  Use date from the MIPS ABI flags structure if present,
and otherwise there may be an MDMX ASE flag set in the ELF file header.
For backwards compatibility only set extra flags and do not clear any,
preserving all previously set by the architecture selected to be
disassembled for.

	include/
	* elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
	typedef as `elf_internal_abiflags_v0'.

	bfd/
	* bfd-in.h (elf_internal_abiflags_v0): New struct declaration.
	(bfd_mips_elf_get_abiflags): New prototype.
	* elfxx-mips.c (bfd_mips_elf_get_abiflags): New function.
	* bfd-in2.h: Regenerate.

	opcodes/
	* mips-dis.c (mips_convert_abiflags_ases): New function.
	(set_default_mips_dis_options): Also infer ASE flags from ELF
	file structures.

	binutils/
	* testsuite/binutils-all/mips/mips-ase-1.d: New test.
	* testsuite/binutils-all/mips/mips-ase-2.d: New test.
	* testsuite/binutils-all/mips/mips-ase-3.d: New test.
	* testsuite/binutils-all/mips/mips-ase-1.s: New test source.
	* testsuite/binutils-all/mips/mips-ase-2.s: New test source.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-14 22:12:21 +00:00
8184783a40 MIPS/opcodes: Reorder ELF file header flag handling in disassembler
Move ELF file header flag interpretation code, used to set disassembler
options, beyond architecture setup.  No functional change as the effects
of both code sections are disjoint from each other, but this provides
for a further expansion of ELF file header flag interpretation.

	opcodes/
	* mips-dis.c (set_default_mips_dis_options): Reorder ELF file
	header flag interpretation code.
2016-12-14 22:09:08 +00:00
eefc336583 MIPS16/GAS: Fix assertion failures with relocations on 16-bit instructions
Complement commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1 branch
relocation support)" and report an assembly error when a relocation is
required for an instruction, currently a branch only, that has been
forced to use its unextended encoding, either with the use of an
explicit `.t' mnemonic suffix, or by means of `.set noautoextend' being
active, fixing an assertion failure currently caused instead.

	gas/
	* config/tc-mips.c (md_convert_frag): Report an error instead of
	asserting on `ext'.
	* testsuite/gas/mips/mips16-branch-unextended-1.d: New test.
	* testsuite/gas/mips/mips16-branch-unextended-2.d: New test.
	* testsuite/gas/mips/mips16-branch-unextended-1.s: New test
	source.
	* testsuite/gas/mips/mips16-branch-unextended-2.s: New test.
	* testsuite/gas/mips/mips16-branch-unextended.l: New stderr
	output.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-14 22:05:38 +00:00
353abf7c10 MIPS16: Fix SP-relative SD instruction annotation
Fix the annotation of SP-relative SD instructions incorrectly marked as
reading from the PC rather than SP, which in turn prevented their 16-bit
forms from being scheduled into jump delay slots.  This bug has been
there since forever.

	opcodes/
	* mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
	`pinfo2' with SP-relative "sd" entries.

	gas/
	* testsuite/gas/mips/mips16-sprel-swap.d: New test.
	* testsuite/gas/mips/mips16-sprel-swap.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new test.
2016-12-14 22:04:39 +00:00
63e014fccd MIPS16/opcodes: Fix and clarify MIPS16e commentary
Correct the note about JALRC/JRC being compact jumps rather than
branches, and add a reference from where the remaining MIPS16e additions
live and the jumps used to be too, complementing commit ceb94aa50d68
("Update insn_mo when converting to a MIPS16e compact jump"),
<https://sourceware.org/ml/binutils/2011-06/msg00369.html>.

	opcodes/
	* mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
	compact jumps.
2016-12-14 22:02:24 +00:00
c1fc2d7ee5 ld: aarch64: fix TLS relaxation where TCB_SIZE is used
TCB_SIZE is 2*sizeof(void *), which is 0x10 for lp64, and 0x8 for
ilp32. During relaxation, ld goes to do a replace:
bl   __tls_get_addr => add R0, R0, TCB_SIZE

But actual implementation is:
bfd_putl32 (0x91004000, contents + rel->r_offset + 4);

Which is equivalent of add x0, x0, 0x10. This is wrong for ilp32.

The possible fix for it is:
bfd_putl32 (0x91000000 | (TCB_SIZE<<10), contents + rel->r_offset + 4);

But ilp32 also needs w-registers, so it's simpler to put proper
instruction in #if/#else condition.

There are 2 such relaxations in elfNN_aarch64_tls_relax(), and so 2 new
tests added for ilp32 mode to test it.

Yury

	* bfd/elfnn-aarch64.c: fix TLS relaxations for ilp32 where
	TCB_SIZE is used.
	* ld/testsuite/ld-aarch64/aarch64-elf.exp: Add tests for the case.
	* ld/testsuite/ld-aarch64/tls-relax-ld-le-small-ilp32.d: New file.
	* ld/testsuite/ld-aarch64/tls-relax-ld-le-tiny-ilp32.d: New file.

Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
2016-12-14 12:00:59 +05:30
7acd51d697 Revert "bfd: aarch64: fix word and arrdess size declaration in ilp32 mode"
This reverts commit a02c3512655cc2c8ad68e4b656959b7d284acc7d.
2016-12-14 11:57:42 +05:30
98fa61facf Revert "ld: aarch64: fix TLS relaxation where TCB_SIZE is used"
This reverts commit 6650f7bd18f8161b9f666d3e65a6346e23a9d85f.
2016-12-14 11:56:54 +05:30
a02c351265 bfd: aarch64: fix word and arrdess size declaration in ilp32 mode 2016-12-14 11:07:24 +05:30
6650f7bd18 ld: aarch64: fix TLS relaxation where TCB_SIZE is used
TCB_SIZE is 2*sizeof(void *), which is 0x10 for lp64, and 0x8 for
ilp32. During relaxation, ld goes to do a replace:
bl   __tls_get_addr => add R0, R0, TCB_SIZE

But actual implementation is:
bfd_putl32 (0x91004000, contents + rel->r_offset + 4);

Which is equivalent of add x0, x0, 0x10. This is wrong for ilp32.

The possible fix for it is:
bfd_putl32 (0x91000000 | (TCB_SIZE<<10), contents + rel->r_offset + 4);

But ilp32 also needs w-registers, so it's simpler to put proper
instruction in #if/#else condition.

THere are 2 such relaxations in elfNN_aarch64_tls_relax(), and so 2 new
tests added for ilp32 mode to test it.

Yury
2016-12-14 11:07:24 +05:30
fc8e0108db Automatic date update in version.in 2016-12-14 00:00:23 +00:00
591be3e4a8 Add --orphan-handling option.
gold/
	PR gold/20749
	* options.h (--orphan-handling): New option.
	(General_options::Orphan_handling): New enum.
	(General_options::orphan_handling_enum): New method.
	(General_options::set_orphan_handling_enum): New method.
	(General_options::orphan_handling_enum_): New data member.
	* options.cc (General_options::General_options): Initialize new member.
	(General_options::finalize): Convert --orphan-handling argument to enum.
	* script-sections.cc (Script_sections::output_section_name): Check it.
2016-12-13 13:01:26 -08:00
03fb64f837 Do not use linker script to place static relocation sections.
gold/
	PR gold/20522
	* layout.cc (Layout::choose_output_section): Add is_reloc parameter.
	Adjust all callers.  Do not use linker script for is_reloc sections.
	(Layout::layout_reloc): Pass is_reloc == true.
	* layout.h (Layout::choose_output_section): Add is_reloc parameter.
2016-12-13 13:01:26 -08:00
a6a5175474 [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field
The internal CN register representation for coprocessor fields used in aarch64
sys, sysl instructions are removed in this patch.

After the change, those fields are represented as immediate. Related checks are
added as well.

opcodes/

	* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
	qualifier.
	(operand_general_constraint_met_p): Remove case for CP_REG.
	(aarch64_print_operand): Print CRn, CRm operand using imm field.
	* aarch64-tbl.h (QL_SYS): Use CR qualifier.
	(QL_SYSL): Likewise.
	(aarch64_opcode_table): Change CRn, CRm operand class and type.
	* aarch64-opc-2.c : Regenerate.
	* aarch64-asm-2.c : Likewise.
	* aarch64-dis-2.c : Likewise.

include/

	* opcode/aarch64.h (aarch64_operand_class): Remove
	AARCH64_OPND_CLASS_CP_REG.
	(enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
	AARCH64_OPND_Cm to AARCH64_OPND_CRm.
	(aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.

gas/

	* config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register.
	(get_reg_expected_msg): Remove CN register case.
	(parse_operands): rewrite parser for CRn, CRm operand.
	(reg_names): Remove CN register.
	* testsuite/gas/aarch64/diagnostic.s: Add a new test case.
	* testsuite/gas/aarch64/diagnostic.l: Adjust error message.
2016-12-13 17:20:08 +00:00
aa785360cf PE linker script improvements.
PR ld/19254
	* scripttempl/pe.sc (.fini): KEEP this section.
	(.gcc_except_table): Likewise.
	(.pdata): Also accept .pdata*.
2016-12-13 17:05:20 +00:00
963201cf5d Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.
sim/aarch64
	* simulator.c (NEG, POS): Move before set_flags_for_add64.
	(set_flags_for_add64): Replace with a modified copy of
	set_flags_for_sub64.

	sim/testsuite/sim/aarch64
	* testutils.inc (pass): Move .Lpass to start.
	(fail): Move .Lfail to start.  Return 1 instead of 0.
	(start): Moved .Lpass and .Lfail to here.
	* adds.s: New.
	* fstur.s: New.
	* tbnz.s: New.
2016-12-13 08:44:31 -08:00
9282b95ab7 [AArch64] Recognize R_AARCH64_P32_ABS32 as 32-bit relocation in readelf
binutils/
	* readelf.c (is_32bit_abs_reloc): Recognize R_AARCH64_P32_ABS32.
2016-12-13 12:52:59 +00:00
971f1d27d2 [AArch64] Make LD testcases support ILP32 mode
ld/
	* testsuite/ld-aarch64/aarch64-elf.exp (aarch64_choose_lp64_emul): New
	function.
	(run_dump_test_lp64): New function which pass LP64 mode options to both
	assembler and linker when building test binary.
	(aarch64elftests): Remove eh-frame-merge test.
	(eh-frame-merge-lp64): Restrict eh-frame-merge test to LP64 only.
	(run_dump_test): Migrate to run_dump_test_lp64 if the test source was
	written for LP64 only.
	* testsuite/ld-aarch64/erratum843419.d: Support ILP32 mode.
	* testsuite/ld-aarch64/farcall-b-defsym.d: Likewise.
	* testsuite/ld-aarch64/farcall-b-plt.d: Likewise.
	* testsuite/ld-aarch64/farcall-b.d: Likewise.
	* testsuite/ld-aarch64/farcall-bl-defsym.d: Likewise.
	* testsuite/ld-aarch64/farcall-bl-plt.d: Likewise.
	* testsuite/ld-aarch64/farcall-bl.d: Likewise.
	* testsuite/ld-aarch64/ifunc-15.d: Likewise.
	* testsuite/ld-aarch64/ifunc-16.d: Likewise.
	* testsuite/ld-aarch64/ifunc-5a-local.d: Likewise.
	* testsuite/ld-aarch64/ifunc-5a.d: Likewise.
	* testsuite/ld-aarch64/ifunc-5b-local.d: Likewise.
	* testsuite/ld-aarch64/ifunc-5b.d: Likewise.
	* testsuite/ld-aarch64/ifunc-5r-local.d: Likewise.
	* testsuite/ld-aarch64/ifunc-6a.d: Likewise.
	* testsuite/ld-aarch64/ifunc-6b.d: Likewise.
	* testsuite/ld-aarch64/ifunc-7a.d: Likewise.
	* testsuite/ld-aarch64/ifunc-7b.d: Likewise.
	* testsuite/ld-aarch64/ifunc-8.d: Likewise.
	* testsuite/ld-aarch64/limit-b.d: Likewise.
	* testsuite/ld-aarch64/limit-bl.d: Likewise.
2016-12-13 12:50:17 +00:00
1bec0c8632 [AArch64] Make GAS testcases support ILP32 mode
gas/
	* gas/testsuite/gas/aarch64/addsub.d: Support ILP32 mode.
	* gas/testsuite/gas/aarch64/advsimd-across.d: Likewise.
	* gas/testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
	* gas/testsuite/gas/aarch64/advsimd-fp16.d: Likewise.
	* gas/testsuite/gas/aarch64/advsimd-misc.d: Likewise.
	* gas/testsuite/gas/aarch64/advsisd-copy.d: Likewise.
	* gas/testsuite/gas/aarch64/advsisd-misc.d: Likewise.
	* gas/testsuite/gas/aarch64/alias.d: Likewise.
	* gas/testsuite/gas/aarch64/armv8-ras-1.d: Likewise.
	* gas/testsuite/gas/aarch64/b_1.d: Likewise.
	* gas/testsuite/gas/aarch64/beq_1.d: Likewise.
	* gas/testsuite/gas/aarch64/bitfield-dump: Likewise.
	* gas/testsuite/gas/aarch64/bitfield-no-aliases.d: Likewise.
	* gas/testsuite/gas/aarch64/codealign.d: Likewise.
	* gas/testsuite/gas/aarch64/codealign_1.d: Likewise.
	* gas/testsuite/gas/aarch64/crc32-directive.d: Likewise.
	* gas/testsuite/gas/aarch64/crc32.d: Likewise.
	* gas/testsuite/gas/aarch64/crypto-directive.d: Likewise.
	* gas/testsuite/gas/aarch64/crypto.d: Likewise.
	* gas/testsuite/gas/aarch64/dwarf.d: Likewise.
	* gas/testsuite/gas/aarch64/float-fp16.d: Likewise.
	* gas/testsuite/gas/aarch64/floatdp2.d: Likewise.
	* gas/testsuite/gas/aarch64/fp-armv8_3.d: Likewise.
	* gas/testsuite/gas/aarch64/fp-const0-parse.d: Likewise.
	* gas/testsuite/gas/aarch64/fp_cvt_int.d: Likewise.
	* gas/testsuite/gas/aarch64/fpmov.d: Likewise.
	* gas/testsuite/gas/aarch64/inst-directive.d: Likewise.
	* gas/testsuite/gas/aarch64/ldr_1.d: Likewise.
	* gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise.
	* gas/testsuite/gas/aarch64/ldst-exclusive.d: Likewise.
	* gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
	* gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
	* gas/testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
	* gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
	* gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
	* gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
	* gas/testsuite/gas/aarch64/lor-directive.d: Likewise.
	* gas/testsuite/gas/aarch64/lor.d: Likewise.
	* gas/testsuite/gas/aarch64/lse-atomic.d: Likewise.
	* gas/testsuite/gas/aarch64/mapmisc.d: Likewise.
	* gas/testsuite/gas/aarch64/mov-no-aliases.d: Likewise.
	* gas/testsuite/gas/aarch64/mov.d: Likewise.
	* gas/testsuite/gas/aarch64/movi.d: Likewise.
	* gas/testsuite/gas/aarch64/movw_label.d: Likewise.
	* gas/testsuite/gas/aarch64/msr.d: Likewise.
	* gas/testsuite/gas/aarch64/neon-fp-cvt-int.d: Likewise.
	* gas/testsuite/gas/aarch64/neon-frint.d: Likewise.
	* gas/testsuite/gas/aarch64/neon-ins.d: Likewise.
	* gas/testsuite/gas/aarch64/neon-not.d: Likewise.
	* gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d: Likewise.
	* gas/testsuite/gas/aarch64/neon-vfp-reglist.d: Likewise.
	* gas/testsuite/gas/aarch64/no-aliases.d: Likewise.
	* gas/testsuite/gas/aarch64/optional.d: Likewise.
	* gas/testsuite/gas/aarch64/pac.d: Likewise.
	* gas/testsuite/gas/aarch64/pan-directive.d: Likewise.
	* gas/testsuite/gas/aarch64/pan.d: Likewise.
	* gas/testsuite/gas/aarch64/rdma-directive.d: Likewise.
	* gas/testsuite/gas/aarch64/rdma.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_g0.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_g0_nc.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_g1.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_hi12.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-1.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-tlsldm-1.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-tlsldm-page-1.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.d: Likewise.
	* gas/testsuite/gas/aarch64/shifted.d: Likewise.
	* gas/testsuite/gas/aarch64/sve.d: Likewise.
	* gas/testsuite/gas/aarch64/symbol.d: Likewise.
	* gas/testsuite/gas/aarch64/sysreg-1.d: Likewise.
	* gas/testsuite/gas/aarch64/sysreg-2.d: Likewise.
	* gas/testsuite/gas/aarch64/sysreg-3.d: Likewise.
	* gas/testsuite/gas/aarch64/sysreg.d: Likewise.
	* gas/testsuite/gas/aarch64/system-2.d: Likewise.
	* gas/testsuite/gas/aarch64/system-3.d: Likewise.
	* gas/testsuite/gas/aarch64/system.d: Likewise.
	* gas/testsuite/gas/aarch64/tbz_1.d: Likewise.
	* gas/testsuite/gas/aarch64/tlbi_op.d: Likewise.
	* gas/testsuite/gas/aarch64/tls.d: Likewise.
	* gas/testsuite/gas/aarch64/uao-directive.d: Likewise.
	* gas/testsuite/gas/aarch64/uao.d: Likewise.
	* gas/testsuite/gas/aarch64/virthostext-directive.d: Likewise.
	* gas/testsuite/gas/aarch64/virthostext.d: Likewise.
	* gas/testsuite/gas/aarch64/adr_1.d: Restrict test under -mabi=lp64.
	* gas/testsuite/gas/aarch64/int-insns.d: Likewise.
	* gas/testsuite/gas/aarch64/programmer-friendly.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-data.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_g1_nc.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_g2.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst16.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst32.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst64.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst8.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst16.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst32.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst64.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst8.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-gotoff_g0_nc.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-gotoff_g1.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-gottprel_g0_nc.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-gottprel_g1.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-insn.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g0_nc.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g1.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-tlsgd_g0_nc.d: Likewise.
	* gas/testsuite/gas/aarch64/reloc-tlsgd_g1.d: Likewise.
	* gas/testsuite/gas/aarch64/tail_padding.d: Likewise.
	* gas/testsuite/gas/aarch64/tls-desc.d: Likewise.
2016-12-13 12:46:35 +00:00
1336427510 Add a 'Past Maintainers' section to the MAINTAINERS file. Retire Mark Mitchell's name to this section.
* MAINTAINERS (Past Maintainers): New section.  Move Mark
	Mitchell's name here.
2016-12-13 11:19:23 +00:00
bfbf34de2f When using linker scripts, place linker-generated sections by the output section name.
2016-12-12  Igor Kudrin  <ikudrin@accesssoftek.com>
	    Cary Coutant  <ccoutant@gmail.com>

gold/
	PR gold/14676
	* script-sections.cc (Output_section_definition::output_section_name):
	For linker-generated sections, compare with output section name.
	* testsuite/Makefile.am (script_test_13): New test.
	* testsuite/Makefile.in: Regenerate.
	* testsuite/script_test_13.c: New source file.
	* testsuite/script_test_13.sh: New script.
	* testsuite/script_test_13.t: New linker script.
2016-12-12 18:52:44 -08:00
d81222d386 Fix edge cases in orphan section placement.
There were still some cases I found where orphan section placement
was screwy -- where the script has no output section description for
either .data or .bss, a .bss orphan section ends up getting placed
before the .data section. In addition, if there is an output section
description for a data section not named .data (e.g., .rela.dyn),
the orphan .bss gets placed before it. This patch cleans that up,
by tracking the last allocated section even as we're adding orphans.

I've also improved segment layout in the absence of a PHDRS clause.
A zero-length NOBITS section will no longer force a new segment
when followed by a PROGBITS section.

2016-12-12  Cary Coutant  <ccoutant@gmail.com>

gold/
	* script-sections.cc (Orphan_section_placement::update_last_alloc):
	New method.
	(Orphan_section_placement::find_place): Place orphan .data section
	after either RODATA or TEXT.
	(Script_sections::place_orphan): Call update_last_alloc for allocated
	sections.
	(Script_sections::create_segments): Improve handling of BSS.
2016-12-12 17:52:53 -08:00
75c6202b1d Automatic date update in version.in 2016-12-13 00:00:25 +00:00
22b05d33b4 Don't add PHDR for objcopy/strip or ld script specifying PHDRS
HPPA64 needs to add a DT_PHDR header for shared libs.  That's fine
when linking but shouldn't happen for strip/objcopy.  Also PHDR must
come first so there's no need to look at all program headers.

bfd/
	* elf64-hppa.c (elf64_hppa_modify_segment_map): Don't add PHDR
	for objcopy/strip or when a ld script specifies PHDRS.
ld/
	* testsuite/ld-elf/nobits-1.d: Remove xfail for hppa64.
	* testsuite/ld-elf/note-1.d: Likewise.
	* testsuite/ld-elf/note-2.d: Likewise.
2016-12-13 09:37:59 +10:30
6392030005 Don't fudge p_vaddr when PHDR in segment
RX does horrible fudges to PT_LOAD p_vaddr, that affect the testsuite
and mean the target won't support dynamic objects.  The latter
probably doesn't matter too much since RX is an embedded target, but
it's easy to stop some of the fudges in order to reduce special cases
for RX in the testsuite.  The changes make sense in isolation too.

bfd/
	* elf32-rx.c (elf32_rx_modify_program_headers): Don't adjust
	segments that include the ELF file header or program headers.
ld/
	* testsuite/ld-elf/flags1.d: Run for RX.
	* testsuite/ld-scripts/phdrs.exp: Likewise.
	* testsuite/ld-scripts/pr14962.d: Likewise.
	* testsuite/ld-scripts/pr14962-2.d: Likewise.
2016-12-13 09:37:37 +10:30
ea0ffd5be2 [GOLD] Allow for larger alignment in script_test_15
PowerPC64 aligns .got to a 256 byte boundary.  This tends to bump the
data segment file size.

	PR gold/16711
	* testsuite/script_test_15a.sh: Allows larger p_filesz.
	* testsuite/script_test_15b.sh: Likewise.
	* testsuite/script_test_15c.sh: Likewise.
2016-12-13 09:32:30 +10:30
d32a48b9f2 [GOLD] Adjust testcase for PowerPC64
Since the linker created .TOC. symbol is placed at roughly .got+32k,
.toc input sections must be placed in or after .got if .toc entries
are accessed using 16-bit signed offset relocs.  crt1.o contains such
a relocation.

	PR gold/20717
	* testsuite/pr20717.t: Add .got output section containing .toc.
2016-12-13 09:31:19 +10:30
88acc2e167 Port c++/78252 from GCC
PR c++/78252
	* cp-demangle.c (struct d_print_info): Add is_lambda_arg field.
	(d_print_init): Initialize it.
	(d_print_comp_inner) <DEMANGLE_COMPONENT_TEMPLATE_PARAM>: Check
	is_lambda_arg for auto.
	<DEMANGLE_COMPONENT_REFERENCE,
	DEMANGLE_COMPONENT_RVALUE_REFERENCE>: Skip smashing check when
	is_lambda_arg.
	<DEMANGLE_COMPONENT_LAMBDA>: Increment is_lambda_arg around arg
	printing.
	* testsuite/demangle-expected: Add lambda auto mangling cases.
2016-12-12 12:52:37 -05:00
d36cab83a9 Remove assert on exec_bfd in cris_delayed_get_disassembler
cris_delayed_get_disassembler has an assert that exec_bfd can't be
NULL, but this assert can be triggered like this,

(gdb) set architecture cris
The target architecture is assumed to be cris
(gdb) disassemble 0x0,+4
Dump of assembler code from 0x0 to 0x4:
   0x00000000:
../../binutils-gdb/gdb/cris-tdep.c:3798: internal-error: int cris_delayed_get_disassembler(bfd_vma, disassemble_info*): Assertion `exec_bfd != NULL' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.

however, cris_get_disassembler does have code to handle the case that
bfd is NULL,

  /* If there's no bfd in sight, we return what is valid as input in all
     contexts if fed back to the assembler: disassembly *with* register
     prefix.  Unfortunately this will be totally wrong for v32.  */
  if (abfd == NULL)
    return print_insn_cris_with_register_prefix;

This patch is to remove this assert.

gdb:

2016-12-12  Yao Qi  <yao.qi@linaro.org>

	PR tdep/20955
	* cris-tdep.c (cris_delayed_get_disassembler): Remove the
	assert.
2016-12-12 09:09:43 +00:00