When providing negative immediate offset (step) values to the JUMPR and
JUMPS opcodes, the resulting instruction contained an incorrect offset.
This commit fixes that behaviour.
This is the same issue that affected the ESP32 code. See previous commit for
more technical detail on the issue.
When providing negative immediate offset (step) values to the JUMPR and
JUMPS opcodes, the resulting instruction contained an incorrect offset.
This commit fixes that behaviour.
According to the technical reference manual (TRM)
[https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf]
the magnitude of the relative shift from the current position is determined
by bit 0-6 of the step field, and the direction is determined by bit 7,
with 0 meaning PC+step, and 1 meaning PC-step.
(For comparion, the ULP C macros in the ESP-IDF implement this as described
in the TRM. All step values passed to the relevant JUMP macros will result in the
instruction step field having bit 7 indicating the sign and bit 0-6 holding the
absolute value of the offset.)
This fix modifies the I_JUMP_REL{R,S} macros to set the step field correctly
for negative immediate values. Since symbols, which are resolved later during
the BFD relocation phase always evaluate to 0 at this stage (from EXPR_VALUE),
this change to the macro only affects the case of immediate values (as can be
seen from all previous test cases resulting in the same listing output as
before). The relocation code (in function esp32ulp_jumprelr_reloc) already did
this correctly for symbols, and thus remains unchanged.
Example of the issue:
For an offset of -2, the step field should have looked as follows:
bit 0-6 = 2 # positive 2
bit 7 = 1 # 1 means negative
However, the result was actually:
bit 0-6 = 126 # negative 2 (two's compliment)
bit 7 = 1 # 1 means negative
This adds a get_DW_UT_name function to dwarfnames using dwarf2.def
for use in binutils readelf to show the unit types in a DWARF5 header.
include/ChangeLog:
Sync with GCC
* dwarf2.def: Add DWARF5 Unit type header encoding macros
DW_UT_FIRST, DW_UT and DW_UT_END.
* dwarf2.h (enum dwarf_unit_type): Removed and define using
DW_UT_FIRST, DW_UT and DW_UT_END macros.
(get_DW_UT_name): New function declaration.
libiberty/ChangeLog:
Sync with GCC
* dwarfnames.c (get_DW_UT_name): Define using DW_UT_FIRST, DW_UT
and DW_UT_END.
(cherry picked from commit d7b477c541bd31045483f37345727bd8335a052a)
We change the previous definition in the IR object to undefweak only
after all LTO symbols have been read.
include/
PR ld/26262
PR ld/26267
* bfdlink.h (bfd_link_info): Add lto_all_symbols_read.
ld/
PR ld/26262
PR ld/26267
* ldlang.c (lang_process): Set lto_all_symbols_read after all
LTO IR symbols have been read.
* plugin.c (plugin_notice): Override the IR definition only if
all LTO IR symbols have been read or the new definition is
non-weak and the the IR definition is weak
* testsuite/ld-plugin/lto.exp: Run PR ld/26262 and ld/26267
tests.
* testsuite/ld-plugin/pr26262a.c: New file.
* testsuite/ld-plugin/pr26262b.c: Likewise.
* testsuite/ld-plugin/pr26262c.c: Likewise.
* testsuite/ld-plugin/pr26267.err: Likewise.
* testsuite/ld-plugin/pr26267a.c: Likewise.
* testsuite/ld-plugin/pr26267b.c: Likewise.
* testsuite/ld-plugin/pr26267c.c: Likewise.
(cherry picked from commit 0e6a3f07f50723d1831291492b96fdf74bcbdc11)
The unprivileged CSR should be controlled by other specific specs rather
than the privileged spec. For example, the debug CSR should be controlled
by the debug spec, and the float CSR should be controlled by the float
spec. User may use assembler options to choose what the debug and other
specs they want, or may encode the versions of specs into the architecture
string directly. Since we haven't decided which one is better, we set the
defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE
in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec
versions for them. However, these PRIV_SPEC_CLASS_NONE will be changed
to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future.
gas/
* config/tc-riscv.c (riscv_csr_class_check): Removed. Move the
checking into riscv_csr_address.
(riscv_csr_version_check): Likewise.
(riscv_csr_address): New function. Return the suitable CSR address
after checking the ISA dependency and versions. Issue warnings if
we find any conflict and -mcsr-check is set. CSR_CLASS_F and
CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
priv spec versions for them.
(reg_csr_lookup_internal): Call riscv_csr_address to find the
suitable CSR address.
* testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the
priv spec warnings here. These warnings are added by accident.
Remove them and only focus on the ISA dependency warnings.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
than the privileged ones.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR.
* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
include/
* opcode/riscv-opc.h: Support the unprivileged CSR. The versions
of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now.
* opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG.
opcodes/
* riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
unprivileged CSR can also be initialized.
The include/opcode/riscv-opc.h file is no longer automatically generated,
so we remove the misleading comments and add new ones. Besides, the CAUSE_*
macros and DECLARE_CAUSE are unused for binutils and gdb. Therefore, remove
them, too.
include/
* opcode/riscv-opc.h: Cleanup and remove the unused macros.
objdump and readelf have one major CTF-related behavioural difference:
objdump can read .ctf sections that contain CTF archives and extract and
dump their members, while readelf cannot. Since the linker often emits
CTF archives, this means that readelf intermittently and (from the
user's perspective) randomly fails to read CTF in files that ld emits,
with a confusing error message wrongly claiming that the CTF content is
corrupt. This is purely because the archive-opening code in libctf was
needlessly tangled up with the BFD code, so readelf couldn't use it.
Here, we disentangle it, moving ctf_new_archive_internal from
ctf-open-bfd.c into ctf-archive.c and merging it with the helper
function in ctf-archive.c it was already using. We add a new public API
function ctf_arc_bufopen, that looks very like ctf_bufopen but returns
an archive given suitable section data rather than a ctf_file_t: the
archive is a ctf_archive_t, so it can be called on raw CTF dictionaries
(with no archive present) and will return a single-member synthetic
"archive".
There is a tiny lifetime tweak here: before now, the archive code could
assume that the symbol section in the ctf_archive_internal wrapper
structure was always owned by BFD if it was present and should always be
freed: now, the caller can pass one in via ctf_arc_bufopen, wihch has
the usual lifetime rules for such sections (caller frees): so we add an
extra field to track whether this is an internal call from ctf-open-bfd,
in which case we still free the symbol section.
include/
* ctf-api.h (ctf_arc_bufopen): New.
libctf/
* ctf-impl.h (ctf_new_archive_internal): Declare.
(ctf_arc_bufopen): Remove.
(ctf_archive_internal) <ctfi_free_symsect>: New.
* ctf-archive.c (ctf_arc_close): Use it.
(ctf_arc_bufopen): Fuse into...
(ctf_new_archive_internal): ... this, moved across from...
* ctf-open-bfd.c: ... here.
(ctf_bfdopen_ctfsect): Use ctf_arc_bufopen.
* libctf.ver: Add it.
binutils/
* readelf.c (dump_section_as_ctf): Support .ctf archives using
ctf_arc_bufopen. Automatically load the .ctf member of such
archives as the parent of all other members, unless specifically
overridden via --ctf-parent. Split out dumping code into...
(dump_ctf_archive_member): ... here, as in objdump, and call
it once per archive member.
(dump_ctf_indent_lines): Code style fix.
This patch adds GNU attribute support to m68k and utilises it to tag the
floating-point calling convention used (hard-float or soft-float). It enables
the linker to ensure linked objects use a consistent floating-point ABI and
allows tools like GDB to infer the ABI used from the ELF file. It is based on
similar work done for PowerPC.
bfd/
* elf32-m68k.c (m68k_elf_merge_obj_attributes): New function.
(elf32_m68k_merge_private_bfd_data): Merge GNU attributes.
binutils/
* readelf.c (display_m68k_gnu_attribute): New function.
(process_arch_specific): Call display_m68k_gnu_attribute for EM_68K.
gas/
* config/tc-m68k.c (m68k_elf_gnu_attribute): New function.
(md_pseudo_table): Handle "gnu_attribute".
* doc/as.texi: Document GNU attribute for M68K.
include/
* elf/m68k.h: Add enum for GNU object attribute with floating point
tag name and values.
ld/
* testsuite/ld-m68k/attr-gnu-4-0.s: New file.
* testsuite/ld-m68k/attr-gnu-4-1.s: Likewise.
* testsuite/ld-m68k/attr-gnu-4-2.s: Likewise.
* testsuite/ld-m68k/attr-gnu-4-00.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-01.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-02.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-10.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-11.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-12.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-20.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-21.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-22.d: Likewise.
* testsuite/ld-m68k/m68k.exp: Run the new tests.
config/
2020-06-24 H.J. Lu <hongjiu.lu@intel.com>
Sync with GCC
2020-05-29 H.J. Lu <hjl.tools@gmail.com>
PR bootstrap/95413
* cet.m4: Replace save_CFLAGS and save_LDFLAGS with
cet_save_CFLAGS and cet_save_LDFLAGS.
include/
2020-06-24 H.J. Lu <hongjiu.lu@intel.com>
Sync with GCC
2020-06-23 Nick Alcock <nick.alcock@oracle.com>
* libiberty.h (bsearch_r): New.
2020-04-17 Martin Liska <mliska@suse.cz>
Jonathan Yong <10walls@gmail.com>
PR gcov-profile/94570
* filenames.h (defined): Do not define HAVE_DOS_BASED_FILE_SYSTEM
for CYGWIN.
libiberty/
2020-06-23 Nick Alcock <nick.alcock@oracle.com>
* bsearch_r.c: New file.
* Makefile.in (CFILES): Add bsearch_r.c.
(REQUIRED_OFILES): Add bsearch_r.o.
* functions.texi: Regenerate.
2020-05-29 H.J. Lu <hjl.tools@gmail.com>
PR bootstrap/95413
* configure: Regenerated.
2020-05-15 Iain Buclaw <ibuclaw@gdcproject.org>
* d-demangle.c (dlang_attributes): Add @live attribute.
* testsuite/d-demangle-expected: Add new tests.
2020-05-14 Rainer Schuetze <r.sagitario@gmx.de>
Iain Buclaw <ibuclaw@gdcproject.org>
* d-demangle.c (enum dlang_symbol_kinds): Remove enum.
(struct dlang_info): New struct
(dlang_decode_backref): New function.
(dlang_backref): New function.
(dlang_symbol_backref): New function.
(dlang_type_backref): New function.
(dlang_symbol_name_p): New function.
(dlang_function_type_noreturn): New function.
(dlang_function_type): Add 'info' parameter. Decode function type
with dlang_function_type_noreturn.
(dlang_function_args): Add 'info' parameter.
(dlang_type): Add 'info' parameter. Handle back referenced types.
(dlang_identifier): Replace 'kind' parameter with 'info'. Handle back
referenced symbols. Split off decoding of plain identifiers to...
(dlang_lname): ...here.
(dlang_parse_mangle): Replace 'kind' parameter with 'info'. Decode
function type and return with dlang_type.
(dlang_parse_qualified): Replace 'kind' parameter with 'info', add
'suffix_modifier' parameter. Decode function type with
dlang_function_type_noreturn.
(dlang_parse_tuple): Add 'info' parameter.
(dlang_template_symbol_param): New function.
(dlang_template_args): Add 'info' parameter. Decode symbol parameter
with dlang_template_symbol_param. Handle back referenced values, and
externally mangled parameters.
(dlang_parse_template): Add 'info' parameter.
(dlang_demangle_init_info): New function.
(dlang_demangle): Initialize and pass 'info' parameter.
* testsuite/d-demangle-expected: Add new tests.
bfd
* mach-o.c: Support the new load commands by reading a linkedit data
command for them.
binutils
* od-macho.c: Dump linkedit data for new load commands.
include
* mach-o/loader.h: Add declarations of two new Mach-O load
commands.
We do know some conflicts among different privileged specs. For linker,
the safest approach is that don't allow the object linked with others which
may cause conflicts. But this may cause inconvenience since not all objects
with conflicting priv specs are linked will cause problems. But it is hard
to know the detailed conflict cases for linker, so we probably need a option
to tell linker that we do know there are no conflicts, or we are willing to
take risks to link the objects with conflicted priv specs. But the option
is still under discussion.
Therefore, we can report warnings rather than errors when linking the objects
with conflicted priv specs. This not only makes the linker more flexible,
but also warns people that the conflicts may happen. We also need to update
the output priv spec version once the input priv spec is newer.
bfd/
* elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from
opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker.
(riscv_get_priv_spec_class): Likewise.
(riscv_get_priv_spec_name): Likewise.
(riscv_get_priv_spec_class_from_numbers): New function, convert
the version numbers into string, then call riscv_get_priv_spec_class
to get the priv spec class.
* elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration
from include/opcode/riscv.h to bfd/elfxx-riscv.h.
(riscv_get_priv_spec_name): Likewise.
(riscv_get_priv_spec_class_from_numbers): New forward declaration.
(opcode/riscv.h): Include it in the header rather than elfxx-riscv.c.
* elfnn-riscv.c (riscv_merge_attributes): Get the priv spec classes
of input and output objects form their priv spec attributes by
riscv_get_priv_spec_class_from_numbers. Report warning rather than
errors when linking objects with differnet priv spec versions. We do
know v1.9.1 may have conflicts to other versions, so report the
warning, too. After that, update the output priv spec version to the
newest one so far.
gas/
* config/tc-riscv.c (buf_size, buf): Remove the unused variables.
(riscv_set_default_priv_spec): Get the priv spec version from the
priv spec attributes by riscv_get_priv_spec_class_from_numbers.
include/
* opcode/riscv.h (riscv_get_priv_spec_class): Move the function
forward declarations to bfd/elfxx-riscv.h.
(riscv_get_priv_spec_name): Likewise.
opcodes/
* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
* riscv-dis.c: Include elfxx-riscv.h.
ld/
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
2020-06-15 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* elf32-xtensa.c (XSHAL_ABI, XTHAL_ABI_UNDEFINED)
(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros.
(elf32xtensa_abi): New global variable.
(xtensa_abi_choice): New function.
(elf_xtensa_create_plt_entry): Use xtensa_abi_choice instead of
XSHAL_ABI to select PLT code.
gas/
* config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(option_abi_windowed, option_abi_call0): New enum constants.
(md_longopts): Add entries for --abi-windowed and --abi-call0.
(md_parse_option): Add handlers for --abi-windowed and
--abi-call0.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
* doc/as.texi (Target Xtensa options): Add --abi-windowed and
--abi-call0 to the list of options.
* doc/c-xtensa.texi: Add description for options --abi-windowed
and --abi-call0.
* testsuite/gas/xtensa/abi-call0.d: New test definition.
* testsuite/gas/xtensa/abi-windowed.d: New test definition.
* testsuite/gas/xtensa/abi.s: New test source.
include/
* elf/xtensa.h (xtensa_abi_choice): New declaration.
ld/
* emultempl/xtensaelf.em (XSHAL_ABI): Remove macro definition.
(XTHAL_ABI_UNDEFINED, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(xt_config_info_unpack_and_check): Set elf32xtensa_abi if it is
undefined. Use xtensa_abi_choice instead of XSHAL_ABI to test
ABI tag consistency.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
(PARSE_AND_LIST_PROLOGUE): Define OPTION_ABI_WINDOWED,
OPTION_ABI_CALL0 and declare elf32xtensa_abi.
(PARSE_AND_LIST_LONGOPTS): Add entries for --abi-windowed and
--abi-call0.
(PARSE_AND_LIST_OPTIONS): Add help text for --abi-windowed and
--abi-call0.
(PARSE_AND_LIST_ARGS_CASES): Add handlers for --abi-windowed and
--abi-call0.
* ld.texi: Add description for options --abi-windowed and
--abi-call0.
There is a conflict between v1.9 and v1.9.1 - CSR MISA address. MISA is
0xf10 in v1.9, but change to 0x301 in v1.9.1. The change made MISA writable,
but may also cause risk of compatibility. Binutils already support the
-mpriv-spec options and ELF priv attributes, which can used to choose what
privileged spec you want, and then give a correponding CSR name and address
to use. But Gdb and other tools don't have the simialr mechanism for now.
However, there are two things can be confirmed,
1. If we don't have a way to control the priv specs, then the changes, like
MISA, will cause risk and hard to maintain.
2. We get the guarantee that the CSR address won't be reused in the future
specs, even if it is dropped.
I'm not sure if Gdb needs to care about the priv spec versions, it is still
discussing. But drop the priv spec v1.9, and make sure that we won't reuse
the CSR address is a useful solution for now. Also, we might drop the v1.9.1
in a year or two. After that, specs above v1.10 should be compatible anyway.
gas/
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
include/
* opcode/riscv-opc.h: Update the defined versions of CSR from
PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1. Also, drop the
MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9.
* opcode/riscv.h (enum riscv_priv_spec_class): Remove
PRIV_SPEC_CLASS_1P9.
opcodes/
* riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
Prior to this patch, the information describing the AArch64 system
registers was separate from the information describing which system
registers are available depending on the CPU feature set. Indeed, the
latter was implemented as a separate function from the main table with
the system register information.
This patch remedies this situation and puts the feature information into
the system register table itself.
This has several advantages:
* Having all the information described in one place is easier to
maintain.
* The logic to check whether a system register is supported now becomes
trivial (and much more efficient).
Since this patch ended up touching every line of the system register
table, I took the opportunity to make the formatting more consistent and
remove some redundant comments.
Note that there is still more refactoring that could be done along the
same lines here (e.g. with the TLB instructions) but this seemed like a
reasonable first pass.
Testing:
* Regression tested an x64 -> aarch64-none-elf cross binutils.
* Built aarch64-none-elf cross toolchain, checked newlib startup
code still works.
* Bootstrapped binutils on aarch64-linux-gnu, regression tested.
* Built aarch64 kernel using new binutils with allyesconfig.
OK for master? If so, I'll need a maintainer to commit on my behalf
since I don't have write access.
Thanks,
Alex
---
include/ChangeLog:
2020-06-11 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (aarch64_sys_reg): Add required features to struct
describing system registers.
opcodes/ChangeLog:
2020-06-11 Alex Coplan <alex.coplan@arm.com>
* aarch64-opc.c (SYSREG): New macro for describing system registers.
(SR_CORE): Likewise.
(SR_FEAT): Likewise.
(SR_RNG): Likewise.
(SR_V8_1): Likewise.
(SR_V8_2): Likewise.
(SR_V8_3): Likewise.
(SR_V8_4): Likewise.
(SR_PAN): Likewise.
(SR_RAS): Likewise.
(SR_SSBS): Likewise.
(SR_SVE): Likewise.
(SR_ID_PFR2): Likewise.
(SR_PROFILE): Likewise.
(SR_MEMTAG): Likewise.
(SR_SCXTNUM): Likewise.
(aarch64_sys_regs): Refactor to store feature information in the table.
(aarch64_sys_reg_supported_p): Collapse logic for system registers
that now describe their own features.
(aarch64_pstatefield_supported_p): Likewise.
DT_MIPS_OPTIONS is not a regular array as assumed by readelf. This
patch corrects that assumption, and to do so easily, makes various
internal (host byte order) structs the same size as external (target
byte order) structs.
include/
* elf/mips.h (Elf32_RegInfo): Use fixed width integer types.
(Elf64_Internal_RegInfo, Elf_Internal_Options): Likewise.
binutils/
* readelf.c (process_mips_specific): Assert size of internal
types match size of external types, and simplify allocation of
internal buffer. Catch possible integer overflow when sanity
checking option size. Don't assume options are a regular array.
Sanity check reginfo option against option size. Use PRI macros
when printing.
These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value. These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.
The process of writing an instruction to the object file is:
a) cgen_put_insn_value ;; Writes out the opcodes.
b) ARCH_cgen_insert_operand
insert_normal
insert_1
cgen_put_insn_value ;; Writes out the bytes of the
;; operand.
Likewise, the process of reading an instruction from the object file
is:
a) cgen_get_insn_value ;; Reads the opcodes.
b) ARCH_cgen_extract_operand
extract_normal
extract_1
cgen_get_insn_value ;; Reads in the bytes of the
;; operand.
As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.
This is problematic for architectures in which the endianness of
instructions is different to the endianness of data. An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.
This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate. Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.
A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value. It has been adapted to
pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
It has been adapted to pass the new endianargument. Ditto for a
call in the assembler.
Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.
include/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/cgen.h: Get an `endian' argument in both
cgen_get_insn_value and cgen_put_insn_value.
opcodes/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
(cgen_put_insn_value): Likewise.
(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
* cgen-dis.in (print_insn): Likewise.
* cgen-ibld.in (insert_1): Likewise.
(insert_1): Likewise.
(insert_insn_normal): Likewise.
(extract_1): Likewise.
* bpf-dis.c: Regenerate.
* bpf-ibld.c: Likewise.
* bpf-ibld.c: Likewise.
* cgen-dis.in: Likewise.
* cgen-ibld.in: Likewise.
* cgen-opc.c: Likewise.
* epiphany-dis.c: Likewise.
* epiphany-ibld.c: Likewise.
* fr30-dis.c: Likewise.
* fr30-ibld.c: Likewise.
* frv-dis.c: Likewise.
* frv-ibld.c: Likewise.
* ip2k-dis.c: Likewise.
* ip2k-ibld.c: Likewise.
* iq2000-dis.c: Likewise.
* iq2000-ibld.c: Likewise.
* lm32-dis.c: Likewise.
* lm32-ibld.c: Likewise.
* m32c-dis.c: Likewise.
* m32c-ibld.c: Likewise.
* m32r-dis.c: Likewise.
* m32r-ibld.c: Likewise.
* mep-dis.c: Likewise.
* mep-ibld.c: Likewise.
* mt-dis.c: Likewise.
* mt-ibld.c: Likewise.
* or1k-dis.c: Likewise.
* or1k-ibld.c: Likewise.
* xc16x-dis.c: Likewise.
* xc16x-ibld.c: Likewise.
* xstormy16-dis.c: Likewise.
* xstormy16-ibld.c: Likewise.
gas/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen.c (gas_cgen_finish_insn): Pass the endianness to
cgen_put_insn_value.
(gas_cgen_md_apply_fix): Likewise.
(gas_cgen_md_apply_fix): Likewise.
* config/tc-bpf.c (md_apply_fix): Pass data endianness to
cgen_put_insn_value.
* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
cgen_put_insn_value.
cpu/ChangeLog:
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* mep.opc (print_slot_insn): Pass the insn endianness to
cgen_get_insn_value.
This patch adds support for a new CGEN_OPEN_INSN_ENDIAN argument
for @arch@_cgen_cpu_open. This is useful for architectures in
which the endianness of the instruction words is not the same
than the endianness used for data.
An accompanying patch has been sent to the CGEN mailing list that
adds support for this argument on the CGEN side [1]. Its been
already pre-approved [2], and will be applied simultaneously with
this binutils series.
[1] https://sourceware.org/pipermail/cgen/2020q2/002733.html
[2] https://sourceware.org/pipermail/cgen/2020q2/002737.html
include/ChangeLog:
2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
* opcode/cgen.h (enum cgen_cpu_open_arg): New value
CGEN_CPU_OPEN_INSN_ENDIAN.
opcodes/ChangeLog:
2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
* cgen-dis.in (cpu_desc_list): New field `insn_endian'.
(print_insn_): Handle instruction endian.
* bpf-dis.c: Regenerate.
* bpf-desc.c: Regenerate.
* epiphany-dis.c: Likewise.
* epiphany-desc.c: Likewise.
* fr30-dis.c: Likewise.
* fr30-desc.c: Likewise.
* frv-dis.c: Likewise.
* frv-desc.c: Likewise.
* ip2k-dis.c: Likewise.
* ip2k-desc.c: Likewise.
* iq2000-dis.c: Likewise.
* iq2000-desc.c: Likewise.
* lm32-dis.c: Likewise.
* lm32-desc.c: Likewise.
* m32c-dis.c: Likewise.
* m32c-desc.c: Likewise.
* m32r-dis.c: Likewise.
* m32r-desc.c: Likewise.
* mep-dis.c: Likewise.
* mep-desc.c: Likewise.
* mt-dis.c: Likewise.
* mt-desc.c: Likewise.
* or1k-dis.c: Likewise.
* or1k-desc.c: Likewise.
* xc16x-dis.c: Likewise.
* xc16x-desc.c: Likewise.
* xstormy16-dis.c: Likewise.
* xstormy16-desc.c: Likewise.
binutils/ChangeLog:
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* objdump.c (disassemble_data): Set disasm_info.endian_code to
disasm_info.endian after the latter is initialized to the
endianness reported by BFD.
The original report is as follow,
https://sourceware.org/pipermail/binutils/2020-June/111383.html
Inlcude the bfd.h in the include/opcode/riscv.h may cause gdbserver fail
to build. I just want to use the `bfd_boolean` in the opcodes/riscv-opc.c,
but I didn't realize this cause the build failed. Fortunately, I can also
use the `int` as the function return types just like others in the
opcodes/riscv-opc.c.
include/
* opcode/riscv.h: Remove #include "bfd.h". And change the return
types of riscv_get_isa_spec_class and riscv_get_priv_spec_class
from bfd_boolean to int.
opcodes/
* riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
(riscv_get_priv_spec_class): Likewise.
Since this value is used in fields of type tilepro_pipeline (as
NO_PIPELINE, see tc-tilepro.c) it is appropriate to put it in
the tilepro_pipelen enum. This avoids a warning about converting from
one enum type to another.
PR 26044
* opcode/tilepro.h (TILEPRO_NUM_PIPELINE_ENCODINGS): Move to
tilepro_pipeline enum.
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.
2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.
3. Spilt the patches to reduce the burdens of review.
[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.
[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.
4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.
include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
(enum riscv_isa_spec_class): New enum class. All supported ISA spec
belong to one of the class
(struct riscv_ext_version): New structure holds version information
for the specific ISA.
* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
define_version and abort_version. The define_version means which
privilege spec is started to define the CSR, and the abort_version
means which privilege spec is started to abort the CSR. If the CSR is
valid for the newest spec, then the abort_version should be
PRIV_SPEC_CLASS_DRAFT.
(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
* opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
the current supported privilege spec versions.
(struct riscv_csr_extra): Add new fields to store more information
about the CSR. We use these information to find the suitable CSR
address when user choosing a specific privilege spec.
binutils * dwarf.c: Updated since DECLARE_CSR is changed.
opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store
all information about the supported spec and the corresponding ISA
versions. Currently, only Zicsr is supported to verify the
correctness of Z sub extension settings. Others will be supported
in the future patches.
(struct isa_spec_t, isa_specs): List for all supported ISA spec
classes and the corresponding strings.
(riscv_get_isa_spec_class): New function. Get the corresponding ISA
spec class by giving a ISA spec string.
* riscv-opc.c (struct priv_spec_t): New structure.
(struct priv_spec_t priv_specs): List for all supported privilege spec
classes and the corresponding strings.
(riscv_get_priv_spec_class): New function. Get the corresponding
privilege spec class by giving a spec string.
(riscv_get_priv_spec_name): New function. Get the corresponding
privilege spec string by giving a CSR version class.
* riscv-dis.c: Updated since DECLARE_CSR is changed.
* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
according to the chosen version. Build a hash table riscv_csr_hash to
store the valid CSR for the chosen pirv verison. Dump the direct
CSR address rather than it's name if it is invalid.
(parse_riscv_dis_option_without_args): New function. Parse the options
without arguments.
(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
parse the options without arguments first, and then handle the options
with arguments. Add the new option -Mpriv-spec, which has argument.
* riscv-dis.c (print_riscv_disassembler_options): Add description
about the new OBJDUMP option.
ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
priv attributes according to the -mpriv-spec option.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
get_default_version. It is used to find the default version for
the specific extension.
* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
default_major_version and default_minor_version. Add new bfd_boolean
parameter *use_default_version. Set it to TRUE if we need to call
the callback rps->get_default_version to find the default version.
(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
the default version in riscv_parsing_subset_version, and then call
riscv_add_subset to add the subset into subset list.
(riscv_parse_prefixed_ext): Likewise.
(riscv_std_z_ext_strtab): Support Zicsr extensions.
* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
strings rather than characters.
riscv_merge_arch_attr_info): The callback function get_default_version
is only needed for assembler, so set it to NULL int the linker.
* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
* elfxx-riscv.h: Updated.
gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
Static variables which are used to set the ISA extensions. You can
use -march (or ELF build attributes) and -misa-spec to set them,
respectively.
(ext_version_hash): The hash table used to handle the extensions
with versions.
(init_ext_version_hash): Initialize the ext_version_hash according
to riscv_ext_version_table.
(riscv_get_default_ext_version): The callback function of
riscv_parse_subset_t. According to the choosed ISA spec,
get the default version for the specific extension.
(riscv_set_arch): Set the callback function.
(enum options, struct option md_longopts): Add new option -misa-spec.
(md_parse_option): Do not call riscv_set_arch for -march. We will
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
to set default_isa_spec class.
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
ext_version_hash, and then call riscv_set_arch to set the architecture
with versions according to default_arch_with_ext.
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
x extensions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
already set it's version to 2p1 by march, so no need to use the default
2p2 version. For m-ext, we do not set the version by -march and ELF arch
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
ISA spec 2p2, so set 0p0 to it.
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
zicsr is 2p0 according to ISA spec 20191213.
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
You can set them by configure options --with-arch and
--with-isa-spec, respectively.
(riscv_set_default_isa_spec): New function used to set the
default ISA spec.
(md_parse_option): Call riscv_set_default_isa_spec rather than
call riscv_get_isa_spec_class directly.
(riscv_after_parse_args): If the -isa-spec is not set, then we
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
calling riscv_set_default_isa_spec.
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
the --with-isa-spec may be set to different ISA spec.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* configure.ac: Add configure options, --with-arch and
--with-isa-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (default_priv_spec): Static variable which is
used to check if the CSR is valid for the chosen privilege spec. You
can use -mpriv-spec to set it.
(enum reg_class): We now get the CSR address from csr_extra_hash rather
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
(riscv_init_csr_hashes): Only need to initialize one hash table
csr_extra_hash.
(riscv_csr_class_check): Change the return type to void. Don't check
the ISA dependency if -mcsr-check isn't set.
(riscv_csr_version_check): New function. Check and find the CSR address
from csr_extra_hash, according to default_priv_spec. Report warning
for the invalid CSR if -mcsr-check is set.
(reg_csr_lookup_internal): Updated.
(reg_lookup_internal): Likewise.
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
(md_parse_option): Call riscv_set_default_priv_version to set
default_priv_spec.
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
privilege spec to the newest one.
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
include/opcode/riscv.h.
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
to check the ISA dependency for CSR, so fix the spec version by adding
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
privilege spec.
(md_parse_option): Call riscv_set_default_priv_spec rather than
call riscv_get_priv_spec_class directly.
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
calling riscv_set_default_priv_spec.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
the --with-priv-spec may be set to different privilege spec.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* configure.ac: Add configure option --with-priv-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
explicit_attr. Set it to TRUE if any ELF attribute is found.
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
the priv attributes are set.
(md_assemble): Set the default_priv_spec according to the priv
attributes when we start to assemble instruction.
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
riscv_write_out_attrs. Update the arch and priv attributes. If we
don't set the corresponding ELF attributes, then try to output the
default ones.
(riscv_set_public_attributes): If any ELF attribute or -march-attr
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
to update the arch and priv attributes.
(s_riscv_attribute): Make sure all arch and priv attributes are set
before any instruction.
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
ELF attribute or -march-attr is set. If the priv attributes are not
set, then try to update them by the default setting (-mpriv-spec or
--with-priv-spec).
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
set by priv attributes must be supported.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
priv attributes according to the -mpriv-spec option.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.
Now that ISA3.1 is out we can finish with the powerxx silliness.
bfd/
* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
renaming.
* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
* powerpc.cc: Rename powerxx to power10 throughout.
include/
* elf/ppc64.h: Update comment.
* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/ld-powerpc/notoc2.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Likewise.
* testsuite/ld-powerpc/tlsgd.d: Likewise.
* testsuite/ld-powerpc/tlsie.d: Likewise.
* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power10" entry.
(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
* ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
When a coredump is generated, there are a few registers in
ARC HS that are put under a special section, namely ".reg-v2".
It is for backward compatibility reasons with older tools that
we have decided not to extend the generic ".reg" section.
This patch makes it possible to display the information better
regarding that section. Compare the output of "readelf" without
and with these changes:
$ readelf -n core # without the patch
...
LINUX 0x0000000c Unknown note type: (0x00000600)
description data: 78 08 00 00 2f 6c 64 2d 75 43 6c 69
$ readelf -n core # with the patch
...
LINUX 0x0000000c NT_ARC_V2 (ARC HS accumulator/extra registers)
description data: 78 08 00 00 2f 6c 64 2d 75 43 6c 69
In another commit (soon to be submitted), GDB will makes use of these
changes to parse the extra section and its registers.
bfd/ChangeLog
2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com>
* elf-bfd.h (elfcore_write_arc_v2): Add prototype.
* elf.c (elfcore_grok_arc_v2): New function.
(elfcore_grok_note): Call the new function to handle the corresponding
note.
(elfcore_write_arc_v2): New function.
(elfcore_write_register_note): Call the new function to handle the
corresponding pseudo-sections.
binutils/ChangeLog
2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com>
* readelf.c (get_note_type): Handle NT_ARC_V2.
include/elf/ChangeLog
2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com>
* common.h (NT_ARC_V2): New macro definitions.
Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences
(subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32}
for negative differences (subtracted symbol follows diminished symbol).
Don't generate XTENSA_DIFF relocations in the assembler, generate
XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position.
Handle XTENSA_DIFF in BFD for compatibility with old object files.
Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value
as unsigned.
2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* bfd-in2.h: Regenerated.
* elf32-xtensa.c (elf_howto_table): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
(elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc)
(relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and
R_XTENSA_NDIFF{8,16,32}.
* libbfd.h (bfd_reloc_code_real_names): Add names for
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
* reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32}
and BFD_RELOC_XTENSA_NDIFF{8,16,32}.
binutils/
* readelf.c (is_none_reloc): Recognize
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
gas/
* config/tc-xtensa.c (md_apply_fix): Replace
BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
with BFD_RELOC_XTENSA_PDIFF16 in the expected output.
include/
* elf/xtensa.h (elf_xtensa_reloc_type): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
ld/
* testsuite/ld-xtensa/relax-loc.d: New test definition.
* testsuite/ld-xtensa/relax-loc.s: New test source.
* testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
git commit 211dc24b87 removed most sh5 and sh64 SuperH support, after
they were obsoleted by git commit 2b213129c5. This patch removes a
few remaining pieces that should have gone with 211dc24b87.
include/
* elf/sh.h (STO_SH5_ISA32, SHF_SH5_ISA32, SHF_SH5_ISA32_MIXED),
(SHT_SH5_CR_SORTED, STT_DATALABEL): Delete.
bfd/
* elf32-sh.c (sh_elf_relocate_section): Remove STO_SH5_ISA32
processing.
