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[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification) The Branch Target Identification instructions (BTI) are allocated to existing HINT space, using HINT numbers 32, 34, 36, 38, such that bits[7:6] of the instruction identify the compatibility of the BTI instruction to different branches. BTI {<targets>} where <targets> one of the following, specifying which type of indirection is allowed: j : Can be a target of any BR Xn isntruction. c : Can be a target of any BLR Xn and BR {X16|X17}. jc: Can be a target of any free branch. A BTI instruction without any <targets> is the strictest of all and can not be a target of nay free branch. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BTI): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default. (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET. (HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to define HINT #imm values. (HINT_OPD_JC, HINT_OPD_NULL): Likewise. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New. (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag with the hint immediate. * aarch64-opc.c (aarch64_hint_options): New entries for c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI. (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET while checking for HINT_OPD_F_NOPRINT flag. * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to extract value. * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New. (aarch64_opcode_table): Add entry for BTI. (AARCH64_OPERANDS): Add new description for BTI targets. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_bti_operand): New. (process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET. (parse_operands): Likewise. * testsuite/gas/aarch64/system.d: Update for BTI. * testsuite/gas/aarch64/bti.s: New. * testsuite/gas/aarch64/bti.d: New. * testsuite/gas/aarch64/illegal-bti.d: New. * testsuite/gas/aarch64/illegal-bti.l: New.
This commit is contained in:
Sudakshina Das
committed by
Richard Earnshaw
Richard Earnshaw
parent
af4bcb4ce6
commit
ff6054520c
@ -1,3 +1,14 @@
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (parse_bti_operand): New.
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(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
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(parse_operands): Likewise.
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* testsuite/gas/aarch64/system.d: Update for BTI.
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* testsuite/gas/aarch64/bti.s: New.
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* testsuite/gas/aarch64/bti.d: New.
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* testsuite/gas/aarch64/illegal-bti.d: New.
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* testsuite/gas/aarch64/illegal-bti.l: New.
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (aarch64_features): New "rng" option.
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@ -3933,6 +3933,47 @@ parse_barrier_psb (char **str,
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return 0;
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}
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/* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
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return 0 if successful. Otherwise return PARSE_FAIL. */
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static int
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parse_bti_operand (char **str,
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const struct aarch64_name_value_pair ** hint_opt)
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{
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char *p, *q;
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const struct aarch64_name_value_pair *o;
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p = q = *str;
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while (ISALPHA (*q))
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q++;
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o = hash_find_n (aarch64_hint_opt_hsh, p, q - p);
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if (!o)
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{
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set_fatal_syntax_error
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( _("unknown option to BTI"));
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return PARSE_FAIL;
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}
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switch (o->value)
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{
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/* Valid BTI operands. */
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case HINT_OPD_C:
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case HINT_OPD_J:
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case HINT_OPD_JC:
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break;
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default:
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set_syntax_error
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(_("unknown option to BTI"));
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return PARSE_FAIL;
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}
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*str = q;
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*hint_opt = o;
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return 0;
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}
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/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
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Returns the encoding for the option, or PARSE_FAIL.
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@ -5151,6 +5192,11 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
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case AARCH64_OPND_BARRIER_ISB:
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operand->barrier = aarch64_barrier_options + default_value;
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break;
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case AARCH64_OPND_BTI_TARGET:
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operand->hint_option = aarch64_hint_options + default_value;
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break;
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default:
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break;
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@ -6483,6 +6529,12 @@ sys_reg_ins:
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goto failure;
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break;
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case AARCH64_OPND_BTI_TARGET:
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val = parse_bti_operand (&str, &(info->hint_option));
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if (val == PARSE_FAIL)
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goto failure;
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break;
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default:
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as_fatal (_("unhandled operand code %d"), operands[i]);
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}
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12
gas/testsuite/gas/aarch64/bti.d
Normal file
12
gas/testsuite/gas/aarch64/bti.d
Normal file
@ -0,0 +1,12 @@
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#as: -march=armv8.5-a
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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.*: d503241f bti
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.*: d503245f bti c
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.*: d503249f bti j
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.*: d50324df bti jc
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8
gas/testsuite/gas/aarch64/bti.s
Normal file
8
gas/testsuite/gas/aarch64/bti.s
Normal file
@ -0,0 +1,8 @@
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// Test file for AArch64 bti.
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.text
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bti
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bti c
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bti j
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bti jc
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3
gas/testsuite/gas/aarch64/illegal-bti.d
Normal file
3
gas/testsuite/gas/aarch64/illegal-bti.d
Normal file
@ -0,0 +1,3 @@
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#as: -march=armv8-a
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#source: bti.s
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#error_output: illegal-bti.l
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5
gas/testsuite/gas/aarch64/illegal-bti.l
Normal file
5
gas/testsuite/gas/aarch64/illegal-bti.l
Normal file
@ -0,0 +1,5 @@
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[^:]*: Assembler messages:
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[^:]*:[0-9]+: Error: selected processor does not support `bti'
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[^:]*:[0-9]+: Error: selected processor does not support `bti c'
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[^:]*:[0-9]+: Error: selected processor does not support `bti j'
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[^:]*:[0-9]+: Error: selected processor does not support `bti jc'
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@ -44,13 +44,13 @@ Disassembly of section \.text:
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.*: d50323bf (hint #0x1d|autiasp)
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.*: d50323df (hint #0x1e|autibz)
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.*: d50323ff (hint #0x1f|autibsp)
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.*: d503241f hint #0x20
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.*: d503241f (hint #0x20|bti)
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.*: d503243f hint #0x21
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.*: d503245f hint #0x22
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.*: d503245f (hint #0x22|bti c)
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.*: d503247f hint #0x23
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.*: d503249f hint #0x24
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.*: d503249f (hint #0x24|bti j)
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.*: d50324bf hint #0x25
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.*: d50324df hint #0x26
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.*: d50324df (hint #0x26|bti jc)
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.*: d50324ff hint #0x27
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.*: d503251f hint #0x28
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.*: d503253f hint #0x29
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@ -1,3 +1,12 @@
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
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(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
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(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
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(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
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define HINT #imm values.
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(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
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@ -76,6 +76,8 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_CVADP 0x40000000000ULL
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/* Random Number instructions. */
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#define AARCH64_FEATURE_RNG 0x80000000000ULL
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/* BTI instructions. */
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#define AARCH64_FEATURE_BTI 0x100000000000ULL
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/* Architectures are the sum of the base and extensions. */
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#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
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@ -105,7 +107,8 @@ typedef uint32_t aarch64_insn;
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| AARCH64_FEATURE_FRINTTS \
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| AARCH64_FEATURE_SB \
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| AARCH64_FEATURE_PREDRES \
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| AARCH64_FEATURE_CVADP)
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| AARCH64_FEATURE_CVADP \
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| AARCH64_FEATURE_BTI)
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#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
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@ -285,6 +288,7 @@ enum aarch64_opnd
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AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
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AARCH64_OPND_PRFOP, /* Prefetch operation. */
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AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
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AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
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AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
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AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
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@ -1090,6 +1094,13 @@ struct aarch64_inst
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aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
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};
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/* Defining the HINT #imm values for the aarch64_hint_options. */
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#define HINT_OPD_CSYNC 0x11
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#define HINT_OPD_C 0x22
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#define HINT_OPD_J 0x24
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#define HINT_OPD_JC 0x26
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#define HINT_OPD_NULL 0x00
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/* Diagnosis related declaration and interface. */
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@ -1,3 +1,21 @@
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
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(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
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with the hint immediate.
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* aarch64-opc.c (aarch64_hint_options): New entries for
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c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
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(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
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while checking for HINT_OPD_F_NOPRINT flag.
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* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
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extract value.
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* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
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(aarch64_opcode_table): Add entry for BTI.
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(AARCH64_OPERANDS): Add new description for BTI targets.
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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2018-10-09 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): New entries for
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@ -422,165 +422,166 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1162: /* movz */
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value = 1162; /* --> movz. */
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break;
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case 1208: /* autibsp */
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case 1207: /* autibz */
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case 1206: /* autiasp */
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case 1205: /* autiaz */
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case 1204: /* pacibsp */
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case 1203: /* pacibz */
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case 1202: /* paciasp */
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case 1201: /* paciaz */
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case 1182: /* psb */
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case 1181: /* esb */
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case 1180: /* autib1716 */
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case 1179: /* autia1716 */
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case 1178: /* pacib1716 */
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case 1177: /* pacia1716 */
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case 1176: /* xpaclri */
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case 1175: /* sevl */
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case 1174: /* sev */
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case 1173: /* wfi */
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case 1172: /* wfe */
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case 1171: /* yield */
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case 1209: /* autibsp */
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case 1208: /* autibz */
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case 1207: /* autiasp */
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case 1206: /* autiaz */
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case 1205: /* pacibsp */
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case 1204: /* pacibz */
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case 1203: /* paciasp */
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case 1202: /* paciaz */
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case 1183: /* psb */
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case 1182: /* esb */
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case 1181: /* autib1716 */
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case 1180: /* autia1716 */
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case 1179: /* pacib1716 */
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case 1178: /* pacia1716 */
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case 1177: /* xpaclri */
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case 1176: /* sevl */
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case 1175: /* sev */
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case 1174: /* wfi */
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case 1173: /* wfe */
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case 1172: /* yield */
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case 1171: /* bti */
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case 1170: /* csdb */
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case 1169: /* nop */
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case 1168: /* hint */
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value = 1168; /* --> hint. */
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break;
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case 1186: /* pssbb */
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case 1185: /* ssbb */
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case 1184: /* dsb */
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value = 1184; /* --> dsb. */
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case 1187: /* pssbb */
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case 1186: /* ssbb */
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case 1185: /* dsb */
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value = 1185; /* --> dsb. */
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break;
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case 1197: /* cpp */
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case 1196: /* dvp */
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case 1195: /* cfp */
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case 1194: /* tlbi */
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case 1193: /* ic */
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case 1192: /* dc */
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case 1191: /* at */
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case 1190: /* sys */
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value = 1190; /* --> sys. */
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case 1198: /* cpp */
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case 1197: /* dvp */
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case 1196: /* cfp */
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case 1195: /* tlbi */
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case 1194: /* ic */
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case 1193: /* dc */
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case 1192: /* at */
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case 1191: /* sys */
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value = 1191; /* --> sys. */
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break;
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case 2006: /* bic */
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case 1256: /* and */
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value = 1256; /* --> and. */
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case 2007: /* bic */
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case 1257: /* and */
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value = 1257; /* --> and. */
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break;
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case 1239: /* mov */
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case 1258: /* and */
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value = 1258; /* --> and. */
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case 1240: /* mov */
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case 1259: /* and */
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value = 1259; /* --> and. */
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break;
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case 1243: /* movs */
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case 1259: /* ands */
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value = 1259; /* --> ands. */
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case 1244: /* movs */
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case 1260: /* ands */
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value = 1260; /* --> ands. */
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break;
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case 2007: /* cmple */
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case 1294: /* cmpge */
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value = 1294; /* --> cmpge. */
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case 2008: /* cmple */
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case 1295: /* cmpge */
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value = 1295; /* --> cmpge. */
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break;
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case 2010: /* cmplt */
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case 1297: /* cmpgt */
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value = 1297; /* --> cmpgt. */
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case 2011: /* cmplt */
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case 1298: /* cmpgt */
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value = 1298; /* --> cmpgt. */
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break;
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case 2008: /* cmplo */
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case 1299: /* cmphi */
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value = 1299; /* --> cmphi. */
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case 2009: /* cmplo */
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case 1300: /* cmphi */
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value = 1300; /* --> cmphi. */
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break;
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case 2009: /* cmpls */
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case 1302: /* cmphs */
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value = 1302; /* --> cmphs. */
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case 2010: /* cmpls */
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case 1303: /* cmphs */
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value = 1303; /* --> cmphs. */
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break;
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case 1236: /* mov */
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case 1324: /* cpy */
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value = 1324; /* --> cpy. */
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break;
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case 1238: /* mov */
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case 1237: /* mov */
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case 1325: /* cpy */
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value = 1325; /* --> cpy. */
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break;
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case 2017: /* fmov */
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case 1241: /* mov */
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case 1239: /* mov */
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case 1326: /* cpy */
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value = 1326; /* --> cpy. */
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break;
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case 1231: /* mov */
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case 1338: /* dup */
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value = 1338; /* --> dup. */
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case 2018: /* fmov */
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case 1242: /* mov */
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case 1327: /* cpy */
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value = 1327; /* --> cpy. */
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break;
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case 1233: /* mov */
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case 1230: /* mov */
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case 1232: /* mov */
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case 1339: /* dup */
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value = 1339; /* --> dup. */
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break;
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case 2016: /* fmov */
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case 1235: /* mov */
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case 1234: /* mov */
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case 1231: /* mov */
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case 1340: /* dup */
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value = 1340; /* --> dup. */
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break;
|
||||
case 1234: /* mov */
|
||||
case 1341: /* dupm */
|
||||
value = 1341; /* --> dupm. */
|
||||
case 2017: /* fmov */
|
||||
case 1236: /* mov */
|
||||
case 1341: /* dup */
|
||||
value = 1341; /* --> dup. */
|
||||
break;
|
||||
case 2011: /* eon */
|
||||
case 1343: /* eor */
|
||||
value = 1343; /* --> eor. */
|
||||
case 1235: /* mov */
|
||||
case 1342: /* dupm */
|
||||
value = 1342; /* --> dupm. */
|
||||
break;
|
||||
case 1244: /* not */
|
||||
case 1345: /* eor */
|
||||
value = 1345; /* --> eor. */
|
||||
case 2012: /* eon */
|
||||
case 1344: /* eor */
|
||||
value = 1344; /* --> eor. */
|
||||
break;
|
||||
case 1245: /* nots */
|
||||
case 1346: /* eors */
|
||||
value = 1346; /* --> eors. */
|
||||
case 1245: /* not */
|
||||
case 1346: /* eor */
|
||||
value = 1346; /* --> eor. */
|
||||
break;
|
||||
case 2012: /* facle */
|
||||
case 1351: /* facge */
|
||||
value = 1351; /* --> facge. */
|
||||
case 1246: /* nots */
|
||||
case 1347: /* eors */
|
||||
value = 1347; /* --> eors. */
|
||||
break;
|
||||
case 2013: /* faclt */
|
||||
case 1352: /* facgt */
|
||||
value = 1352; /* --> facgt. */
|
||||
case 2013: /* facle */
|
||||
case 1352: /* facge */
|
||||
value = 1352; /* --> facge. */
|
||||
break;
|
||||
case 2014: /* fcmle */
|
||||
case 1365: /* fcmge */
|
||||
value = 1365; /* --> fcmge. */
|
||||
case 2014: /* faclt */
|
||||
case 1353: /* facgt */
|
||||
value = 1353; /* --> facgt. */
|
||||
break;
|
||||
case 2015: /* fcmlt */
|
||||
case 1367: /* fcmgt */
|
||||
value = 1367; /* --> fcmgt. */
|
||||
case 2015: /* fcmle */
|
||||
case 1366: /* fcmge */
|
||||
value = 1366; /* --> fcmge. */
|
||||
break;
|
||||
case 2016: /* fcmlt */
|
||||
case 1368: /* fcmgt */
|
||||
value = 1368; /* --> fcmgt. */
|
||||
break;
|
||||
case 1229: /* fmov */
|
||||
case 1374: /* fcpy */
|
||||
value = 1374; /* --> fcpy. */
|
||||
break;
|
||||
case 1228: /* fmov */
|
||||
case 1373: /* fcpy */
|
||||
value = 1373; /* --> fcpy. */
|
||||
case 1397: /* fdup */
|
||||
value = 1397; /* --> fdup. */
|
||||
break;
|
||||
case 1227: /* fmov */
|
||||
case 1396: /* fdup */
|
||||
value = 1396; /* --> fdup. */
|
||||
break;
|
||||
case 1229: /* mov */
|
||||
case 1727: /* orr */
|
||||
value = 1727; /* --> orr. */
|
||||
break;
|
||||
case 2018: /* orn */
|
||||
case 1230: /* mov */
|
||||
case 1728: /* orr */
|
||||
value = 1728; /* --> orr. */
|
||||
break;
|
||||
case 1232: /* mov */
|
||||
case 1730: /* orr */
|
||||
value = 1730; /* --> orr. */
|
||||
case 2019: /* orn */
|
||||
case 1729: /* orr */
|
||||
value = 1729; /* --> orr. */
|
||||
break;
|
||||
case 1242: /* movs */
|
||||
case 1731: /* orrs */
|
||||
value = 1731; /* --> orrs. */
|
||||
case 1233: /* mov */
|
||||
case 1731: /* orr */
|
||||
value = 1731; /* --> orr. */
|
||||
break;
|
||||
case 1237: /* mov */
|
||||
case 1793: /* sel */
|
||||
value = 1793; /* --> sel. */
|
||||
case 1243: /* movs */
|
||||
case 1732: /* orrs */
|
||||
value = 1732; /* --> orrs. */
|
||||
break;
|
||||
case 1240: /* mov */
|
||||
case 1238: /* mov */
|
||||
case 1794: /* sel */
|
||||
value = 1794; /* --> sel. */
|
||||
break;
|
||||
case 1241: /* mov */
|
||||
case 1795: /* sel */
|
||||
value = 1795; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
|
||||
@ -622,7 +623,6 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 27:
|
||||
case 28:
|
||||
case 29:
|
||||
case 154:
|
||||
case 155:
|
||||
case 156:
|
||||
case 157:
|
||||
@ -632,7 +632,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 161:
|
||||
case 162:
|
||||
case 163:
|
||||
case 176:
|
||||
case 164:
|
||||
case 177:
|
||||
case 178:
|
||||
case 179:
|
||||
@ -641,8 +641,9 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 182:
|
||||
case 183:
|
||||
case 184:
|
||||
case 188:
|
||||
case 191:
|
||||
case 185:
|
||||
case 189:
|
||||
case 192:
|
||||
return aarch64_ins_regno (self, info, code, inst, errors);
|
||||
case 13:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
||||
@ -654,7 +655,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 31:
|
||||
case 32:
|
||||
case 33:
|
||||
case 193:
|
||||
case 194:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 34:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
@ -686,9 +687,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 77:
|
||||
case 78:
|
||||
case 79:
|
||||
case 151:
|
||||
case 153:
|
||||
case 168:
|
||||
case 152:
|
||||
case 154:
|
||||
case 169:
|
||||
case 170:
|
||||
case 171:
|
||||
@ -696,6 +696,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 173:
|
||||
case 174:
|
||||
case 175:
|
||||
case 176:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 42:
|
||||
case 43:
|
||||
@ -705,10 +706,10 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 46:
|
||||
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
|
||||
case 50:
|
||||
case 142:
|
||||
case 143:
|
||||
return aarch64_ins_fpimm (self, info, code, inst, errors);
|
||||
case 65:
|
||||
case 149:
|
||||
case 150:
|
||||
return aarch64_ins_limm (self, info, code, inst, errors);
|
||||
case 66:
|
||||
return aarch64_ins_aimm (self, info, code, inst, errors);
|
||||
@ -718,10 +719,10 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
return aarch64_ins_fbits (self, info, code, inst, errors);
|
||||
case 70:
|
||||
case 71:
|
||||
case 147:
|
||||
case 148:
|
||||
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
|
||||
case 72:
|
||||
case 146:
|
||||
case 147:
|
||||
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
|
||||
case 73:
|
||||
case 74:
|
||||
@ -759,24 +760,24 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 99:
|
||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||
case 100:
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
case 101:
|
||||
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
case 102:
|
||||
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
|
||||
case 103:
|
||||
case 104:
|
||||
case 105:
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
||||
case 106:
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
||||
case 107:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
||||
case 108:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
||||
case 109:
|
||||
case 110:
|
||||
case 111:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
|
||||
case 112:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
|
||||
case 113:
|
||||
case 114:
|
||||
case 115:
|
||||
@ -789,8 +790,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 122:
|
||||
case 123:
|
||||
case 124:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
|
||||
case 125:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
|
||||
case 126:
|
||||
case 127:
|
||||
case 128:
|
||||
@ -798,48 +799,49 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 130:
|
||||
case 131:
|
||||
case 132:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
|
||||
case 133:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
|
||||
case 134:
|
||||
case 135:
|
||||
case 136:
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
|
||||
case 137:
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
|
||||
case 138:
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
|
||||
case 139:
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
||||
case 140:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
||||
case 141:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
|
||||
case 142:
|
||||
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
|
||||
case 143:
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
|
||||
case 144:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
|
||||
case 145:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
|
||||
case 146:
|
||||
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
|
||||
case 148:
|
||||
case 149:
|
||||
return aarch64_ins_inv_limm (self, info, code, inst, errors);
|
||||
case 150:
|
||||
case 151:
|
||||
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
|
||||
case 152:
|
||||
case 153:
|
||||
return aarch64_ins_sve_scale (self, info, code, inst, errors);
|
||||
case 164:
|
||||
case 165:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||
case 166:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||
case 167:
|
||||
case 168:
|
||||
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
|
||||
case 185:
|
||||
case 186:
|
||||
case 187:
|
||||
case 188:
|
||||
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
||||
case 189:
|
||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 190:
|
||||
case 192:
|
||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 191:
|
||||
case 193:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1312,7 +1312,7 @@ aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
|
||||
for (i = 0; aarch64_hint_options[i].name != NULL; i++)
|
||||
{
|
||||
if (hint_number == aarch64_hint_options[i].value)
|
||||
if (hint_number == HINT_VAL (aarch64_hint_options[i].value))
|
||||
{
|
||||
info->hint_option = &(aarch64_hint_options[i]);
|
||||
return TRUE;
|
||||
|
||||
@ -125,6 +125,7 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BTI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets j/c/jc"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL"},
|
||||
@ -295,17 +296,17 @@ static const unsigned op_enum_table [] =
|
||||
389,
|
||||
411,
|
||||
413,
|
||||
1232,
|
||||
1237,
|
||||
1230,
|
||||
1229,
|
||||
1233,
|
||||
1240,
|
||||
1242,
|
||||
1238,
|
||||
1231,
|
||||
1230,
|
||||
1234,
|
||||
1241,
|
||||
1243,
|
||||
1239,
|
||||
1245,
|
||||
1244,
|
||||
1240,
|
||||
1246,
|
||||
1245,
|
||||
129,
|
||||
};
|
||||
|
||||
|
||||
@ -466,8 +466,13 @@ const struct aarch64_name_value_pair aarch64_barrier_options[16] =
|
||||
|
||||
const struct aarch64_name_value_pair aarch64_hint_options[] =
|
||||
{
|
||||
{ "csync", 0x11 }, /* PSB CSYNC. */
|
||||
{ NULL, 0x0 },
|
||||
/* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
|
||||
{ " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
|
||||
{ "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
|
||||
{ "c", HINT_OPD_C }, /* BTI C. */
|
||||
{ "j", HINT_OPD_J }, /* BTI J. */
|
||||
{ "jc", HINT_OPD_JC }, /* BTI JC. */
|
||||
{ NULL, HINT_OPD_NULL },
|
||||
};
|
||||
|
||||
/* op -> op: load = 0 instruction = 1 store = 2
|
||||
@ -3654,7 +3659,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_BARRIER_PSB:
|
||||
snprintf (buf, size, "%s", opnd->hint_option->name);
|
||||
case AARCH64_OPND_BTI_TARGET:
|
||||
if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
|
||||
snprintf (buf, size, "%s", opnd->hint_option->name);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
||||
@ -220,6 +220,14 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
|
||||
#define F_REG_WRITE (1 << 4) /* Register can only be written to but not
|
||||
read from. */
|
||||
|
||||
/* HINT operand flags. */
|
||||
#define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
|
||||
|
||||
/* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
|
||||
#define HINT_ENCODE(flag, val) ((flag << 8) | val)
|
||||
#define HINT_FLAG(val) (val >> 8)
|
||||
#define HINT_VAL(val) (val & 0xff)
|
||||
|
||||
static inline bfd_boolean
|
||||
operand_has_inserter (const aarch64_operand *operand)
|
||||
{
|
||||
|
||||
@ -2169,6 +2169,8 @@ static const aarch64_feature_set aarch64_feature_sb =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_SB, 0);
|
||||
static const aarch64_feature_set aarch64_feature_predres =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0);
|
||||
static const aarch64_feature_set aarch64_feature_bti =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0);
|
||||
|
||||
|
||||
#define CORE &aarch64_feature_v8
|
||||
@ -2202,6 +2204,7 @@ static const aarch64_feature_set aarch64_feature_predres =
|
||||
#define FRINTTS &aarch64_feature_frintts
|
||||
#define SB &aarch64_feature_sb
|
||||
#define PREDRES &aarch64_feature_predres
|
||||
#define BTI &aarch64_feature_bti
|
||||
|
||||
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
@ -2263,6 +2266,8 @@ static const aarch64_feature_set aarch64_feature_predres =
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define BTI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
|
||||
struct aarch64_opcode aarch64_opcode_table[] =
|
||||
{
|
||||
@ -3510,6 +3515,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS),
|
||||
CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("csdb",0xd503229f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
BTI_INSN ("bti",0xd503241f, 0xffffff3f, ic_system, OP1 (BTI_TARGET), {}, F_ALIAS | F_OPD0_OPT | F_DEFAULT (0x0)),
|
||||
CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
@ -4629,6 +4635,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
"a prefetch operation specifier") \
|
||||
Y(SYSTEM, hint, "BARRIER_PSB", 0, F (), \
|
||||
"the PSB option name CSYNC") \
|
||||
Y(SYSTEM, hint, "BTI", 0, F (), \
|
||||
"BTI targets j/c/jc") \
|
||||
Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \
|
||||
4 << OPD_F_OD_LSB, F(FLD_Rn), \
|
||||
"an address with a 4-bit signed offset, multiplied by 16") \
|
||||
|
||||
Reference in New Issue
Block a user