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PowerPC Improve support for Gekko & Broadway
This is a relatively straightforward patch to improve support for the IBM Gekko and IBM Broadway processors. Broadway is functionally equivalent to the IBM 750CL, while Gekko's functionality is a subset of theirs. The patch simplifies this reality and adds -mgekko and -mbroadway as aliases for -m750cl. I didn't feel it was worth wasting a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of simplified mnemonics for special purpose register access. Notably, Broadway adds 4 additional IBAT and DBAT registers but these are not assigned sequential SPR numbers. gas/ * config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway. * doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * testsuite/gas/ppc/broadway.d, * testsuite/gas/ppc/broadway.s: New test for broadway. * testsuite/gas/ppc/ppc.exp: Run new test. include/ * opcode/ppc.h (PPC_OPCODE_750): Adjust comment. opcodes/ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. (powerpc_init_dialect): Handle bfd_mach_ppc_750. * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to support disjointed BAT. (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. (XSPRGQR_MASK, GEKKO, BROADWAY): Define. (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
This commit is contained in:
Alex Chadwick
committed by
Alan Modra
Alan Modra
parent
b358827438
commit
fa758a7046
@ -1,3 +1,12 @@
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2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
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* config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway.
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* doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway.
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* doc/c-ppc.texi (PowerPC-Opts): Likewise.
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* testsuite/gas/ppc/broadway.d,
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* testsuite/gas/ppc/broadway.s: New test for broadway.
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* testsuite/gas/ppc/ppc.exp: Run new test.
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2018-07-26 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c (ppc_elf_localentry): Allow .localentry values
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@ -1340,7 +1340,8 @@ PowerPC options:\n\
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-m476 generate code for PowerPC 476\n\
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-m7400, -m7410, -m7450, -m7455\n\
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generate code for PowerPC 7400/7410/7450/7455\n\
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-m750cl generate code for PowerPC 750cl\n\
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-m750cl, -mgekko, -mbroadway\n\
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generate code for PowerPC 750cl/Gekko/Broadway\n\
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-m821, -m850, -m860 generate code for PowerPC 821/850/860\n"));
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fprintf (stream, _("\
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-mppc64, -m620 generate code for PowerPC 620/625/630\n\
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@ -476,10 +476,10 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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@emph{Target PowerPC options:}
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[@b{-a32}|@b{-a64}]
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[@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|@b{-m403}|@b{-m405}|
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@b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mppc64}|
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@b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}|
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@b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
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@b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-mpower9}|@b{-mpwr9}@b{-ma2}|
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@b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mgekko}|
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@b{-mbroadway}|@b{-mppc64}|@b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|
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@b{-me6500}|@b{-mppc64bridge}|@b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|
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@b{-mpower6}|@b{-mpwr6}|@b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-mpower9}|@b{-mpwr9}@b{-ma2}|
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@b{-mcell}|@b{-mspe}|@b{-mspe2}|@b{-mtitan}|@b{-me300}|@b{-mcom}]
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[@b{-many}] [@b{-maltivec}|@b{-mvsx}|@b{-mhtm}|@b{-mvle}]
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[@b{-mregnames}|@b{-mno-regnames}]
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@ -72,8 +72,8 @@ Generate code for PowerPC 476.
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@item -m7400, -m7410, -m7450, -m7455
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Generate code for PowerPC 7400/7410/7450/7455.
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@item -m750cl
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Generate code for PowerPC 750CL.
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@item -m750cl, -mgekko, -mbroadway
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Generate code for PowerPC 750CL/Gekko/Broadway.
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@item -m821, -m850, -m860
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Generate code for PowerPC 821/850/860.
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108
gas/testsuite/gas/ppc/broadway.d
Normal file
108
gas/testsuite/gas/ppc/broadway.d
Normal file
@ -0,0 +1,108 @@
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#as: -mbroadway
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#objdump: -dr -Mbroadway
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#name: PPC Broadway instructions
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.*
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Disassembly of section \.text:
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0+0000000 <start>:
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0: (7c 12 fa a6|a6 fa 12 7c) mfiabr r0
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4: (7c 32 fb a6|a6 fb 32 7c) mtiabr r1
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8: (7c 55 fa a6|a6 fa 55 7c) mfdabr r2
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c: (7c 75 fb a6|a6 fb 75 7c) mtdabr r3
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10: (7c 90 e2 a6|a6 e2 90 7c) mfgqr r4,0
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14: (7c b1 e2 a6|a6 e2 b1 7c) mfgqr r5,1
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18: (7c d2 e2 a6|a6 e2 d2 7c) mfgqr r6,2
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1c: (7c f3 e2 a6|a6 e2 f3 7c) mfgqr r7,3
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20: (7d 14 e2 a6|a6 e2 14 7d) mfgqr r8,4
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24: (7d 35 e2 a6|a6 e2 35 7d) mfgqr r9,5
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28: (7d 56 e2 a6|a6 e2 56 7d) mfgqr r10,6
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2c: (7d 77 e2 a6|a6 e2 77 7d) mfgqr r11,7
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30: (7c 90 e3 a6|a6 e3 90 7c) mtgqr 0,r4
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34: (7c b1 e3 a6|a6 e3 b1 7c) mtgqr 1,r5
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38: (7c d2 e3 a6|a6 e3 d2 7c) mtgqr 2,r6
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3c: (7c f3 e3 a6|a6 e3 f3 7c) mtgqr 3,r7
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40: (7d 14 e3 a6|a6 e3 14 7d) mtgqr 4,r8
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44: (7d 35 e3 a6|a6 e3 35 7d) mtgqr 5,r9
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48: (7d 56 e3 a6|a6 e3 56 7d) mtgqr 6,r10
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4c: (7d 77 e3 a6|a6 e3 77 7d) mtgqr 7,r11
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50: (7d 99 e2 a6|a6 e2 99 7d) mfwpar r12
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54: (7d b9 e3 a6|a6 e3 b9 7d) mtwpar r13
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58: (7d db e2 a6|a6 e2 db 7d) mfdmal r14
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5c: (7d fb e3 a6|a6 e3 fb 7d) mtdmal r15
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60: (7e 1a e2 a6|a6 e2 1a 7e) mfdmau r16
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64: (7e 3a e3 a6|a6 e3 3a 7e) mtdmau r17
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68: (7e 50 fa a6|a6 fa 50 7e) mfhid0 r18
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6c: (7e 70 fb a6|a6 fb 70 7e) mthid0 r19
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70: (7e 91 fa a6|a6 fa 91 7e) mfhid1 r20
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74: (7e b1 fb a6|a6 fb b1 7e) mthid1 r21
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78: (7e d8 e2 a6|a6 e2 d8 7e) mfhid2 r22
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7c: (7e f8 e3 a6|a6 e3 f8 7e) mthid2 r23
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80: (7f 13 fa a6|a6 fa 13 7f) mfhid4 r24
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84: (7f 33 fb a6|a6 fb 33 7f) mthid4 r25
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88: (7c 10 82 a6|a6 82 10 7c) mfibatu r0,0
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8c: (7c 30 83 a6|a6 83 30 7c) mtibatu 0,r1
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90: (7c 52 82 a6|a6 82 52 7c) mfibatu r2,1
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94: (7c 72 83 a6|a6 83 72 7c) mtibatu 1,r3
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98: (7c 94 82 a6|a6 82 94 7c) mfibatu r4,2
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9c: (7c b4 83 a6|a6 83 b4 7c) mtibatu 2,r5
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a0: (7c d6 82 a6|a6 82 d6 7c) mfibatu r6,3
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a4: (7c f6 83 a6|a6 83 f6 7c) mtibatu 3,r7
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a8: (7d 10 8a a6|a6 8a 10 7d) mfibatu r8,4
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ac: (7d 30 8b a6|a6 8b 30 7d) mtibatu 4,r9
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b0: (7d 52 8a a6|a6 8a 52 7d) mfibatu r10,5
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b4: (7d 72 8b a6|a6 8b 72 7d) mtibatu 5,r11
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b8: (7d 94 8a a6|a6 8a 94 7d) mfibatu r12,6
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bc: (7d b4 8b a6|a6 8b b4 7d) mtibatu 6,r13
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c0: (7d d6 8a a6|a6 8a d6 7d) mfibatu r14,7
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c4: (7d f6 8b a6|a6 8b f6 7d) mtibatu 7,r15
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c8: (7e 11 82 a6|a6 82 11 7e) mfibatl r16,0
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cc: (7e 31 83 a6|a6 83 31 7e) mtibatl 0,r17
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d0: (7e 53 82 a6|a6 82 53 7e) mfibatl r18,1
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d4: (7e 73 83 a6|a6 83 73 7e) mtibatl 1,r19
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d8: (7e 95 82 a6|a6 82 95 7e) mfibatl r20,2
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dc: (7e b5 83 a6|a6 83 b5 7e) mtibatl 2,r21
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e0: (7e d7 82 a6|a6 82 d7 7e) mfibatl r22,3
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e4: (7e f7 83 a6|a6 83 f7 7e) mtibatl 3,r23
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e8: (7f 11 8a a6|a6 8a 11 7f) mfibatl r24,4
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ec: (7f 31 8b a6|a6 8b 31 7f) mtibatl 4,r25
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f0: (7f 53 8a a6|a6 8a 53 7f) mfibatl r26,5
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f4: (7f 73 8b a6|a6 8b 73 7f) mtibatl 5,r27
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f8: (7f 95 8a a6|a6 8a 95 7f) mfibatl r28,6
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fc: (7f b5 8b a6|a6 8b b5 7f) mtibatl 6,r29
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100: (7f d7 8a a6|a6 8a d7 7f) mfibatl r30,7
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104: (7f f7 8b a6|a6 8b f7 7f) mtibatl 7,r31
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108: (7c 18 82 a6|a6 82 18 7c) mfdbatu r0,0
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10c: (7c 38 83 a6|a6 83 38 7c) mtdbatu 0,r1
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110: (7c 5a 82 a6|a6 82 5a 7c) mfdbatu r2,1
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114: (7c 7a 83 a6|a6 83 7a 7c) mtdbatu 1,r3
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118: (7c 9c 82 a6|a6 82 9c 7c) mfdbatu r4,2
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11c: (7c bc 83 a6|a6 83 bc 7c) mtdbatu 2,r5
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120: (7c de 82 a6|a6 82 de 7c) mfdbatu r6,3
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124: (7c fe 83 a6|a6 83 fe 7c) mtdbatu 3,r7
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128: (7d 18 8a a6|a6 8a 18 7d) mfdbatu r8,4
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12c: (7d 38 8b a6|a6 8b 38 7d) mtdbatu 4,r9
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130: (7d 5a 8a a6|a6 8a 5a 7d) mfdbatu r10,5
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134: (7d 7a 8b a6|a6 8b 7a 7d) mtdbatu 5,r11
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138: (7d 9c 8a a6|a6 8a 9c 7d) mfdbatu r12,6
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13c: (7d bc 8b a6|a6 8b bc 7d) mtdbatu 6,r13
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140: (7d de 8a a6|a6 8a de 7d) mfdbatu r14,7
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144: (7d fe 8b a6|a6 8b fe 7d) mtdbatu 7,r15
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148: (7e 19 82 a6|a6 82 19 7e) mfdbatl r16,0
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14c: (7e 39 83 a6|a6 83 39 7e) mtdbatl 0,r17
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150: (7e 5b 82 a6|a6 82 5b 7e) mfdbatl r18,1
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154: (7e 7b 83 a6|a6 83 7b 7e) mtdbatl 1,r19
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158: (7e 9d 82 a6|a6 82 9d 7e) mfdbatl r20,2
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15c: (7e bd 83 a6|a6 83 bd 7e) mtdbatl 2,r21
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160: (7e df 82 a6|a6 82 df 7e) mfdbatl r22,3
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164: (7e ff 83 a6|a6 83 ff 7e) mtdbatl 3,r23
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168: (7f 19 8a a6|a6 8a 19 7f) mfdbatl r24,4
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16c: (7f 39 8b a6|a6 8b 39 7f) mtdbatl 4,r25
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170: (7f 5b 8a a6|a6 8a 5b 7f) mfdbatl r26,5
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174: (7f 7b 8b a6|a6 8b 7b 7f) mtdbatl 5,r27
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178: (7f 9d 8a a6|a6 8a 9d 7f) mfdbatl r28,6
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17c: (7f bd 8b a6|a6 8b bd 7f) mtdbatl 6,r29
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180: (7f df 8a a6|a6 8a df 7f) mfdbatl r30,7
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184: (7f ff 8b a6|a6 8b ff 7f) mtdbatl 7,r31
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#pass
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103
gas/testsuite/gas/ppc/broadway.s
Normal file
103
gas/testsuite/gas/ppc/broadway.s
Normal file
@ -0,0 +1,103 @@
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# PowerPC Broadway instruction tests
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.text
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start:
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mfiabr 0
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mtiabr 1
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mfdabr 2
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mtdabr 3
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mfgqr 4, 0
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mfgqr 5, 1
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mfgqr 6, 2
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mfgqr 7, 3
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mfgqr 8, 4
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mfgqr 9, 5
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mfgqr 10, 6
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mfgqr 11, 7
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mtgqr 0, 4
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mtgqr 1, 5
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mtgqr 2, 6
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mtgqr 3, 7
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mtgqr 4, 8
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mtgqr 5, 9
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mtgqr 6, 10
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mtgqr 7, 11
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mfwpar 12
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mtwpar 13
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mfdmal 14
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mtdmal 15
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mfdmau 16
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mtdmau 17
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mfhid0 18
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mthid0 19
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mfhid1 20
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mthid1 21
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mfhid2 22
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mthid2 23
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mfhid4 24
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mthid4 25
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mfibatu 0, 0
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mtibatu 0, 1
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mfibatu 2, 1
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mtibatu 1, 3
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mfibatu 4, 2
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mtibatu 2, 5
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mfibatu 6, 3
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mtibatu 3, 7
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mfibatu 8, 4
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mtibatu 4, 9
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mfibatu 10, 5
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mtibatu 5, 11
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mfibatu 12, 6
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mtibatu 6, 13
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mfibatu 14, 7
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mtibatu 7, 15
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mfibatl 16, 0
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mtibatl 0, 17
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mfibatl 18, 1
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mtibatl 1, 19
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mfibatl 20, 2
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mtibatl 2, 21
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mfibatl 22, 3
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mtibatl 3, 23
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mfibatl 24, 4
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mtibatl 4, 25
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mfibatl 26, 5
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mtibatl 5, 27
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mfibatl 28, 6
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mtibatl 6, 29
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mfibatl 30, 7
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mtibatl 7, 31
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mfdbatu 0, 0
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mtdbatu 0, 1
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mfdbatu 2, 1
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mtdbatu 1, 3
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mfdbatu 4, 2
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mtdbatu 2, 5
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mfdbatu 6, 3
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mtdbatu 3, 7
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mfdbatu 8, 4
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mtdbatu 4, 9
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mfdbatu 10, 5
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mtdbatu 5, 11
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mfdbatu 12, 6
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mtdbatu 6, 13
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mfdbatu 14, 7
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mtdbatu 7, 15
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mfdbatl 16, 0
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mtdbatl 0, 17
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mfdbatl 18, 1
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mtdbatl 1, 19
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mfdbatl 20, 2
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mtdbatl 2, 21
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mfdbatl 22, 3
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mtdbatl 3, 23
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mfdbatl 24, 4
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mtdbatl 4, 25
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mfdbatl 26, 5
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mtdbatl 5, 27
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mfdbatl 28, 6
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mtdbatl 6, 29
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mfdbatl 30, 7
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mtdbatl 7, 31
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@ -90,6 +90,7 @@ run_dump_test "spe_ambiguous"
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run_dump_test "altivec"
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run_dump_test "altivec2"
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run_dump_test "altivec3"
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run_dump_test "broadway"
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run_dump_test "booke"
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run_dump_test "e500"
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run_list_test "e500-ill" "-me500"
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@ -1,3 +1,7 @@
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2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
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* opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
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2018-07-26 Alan Modra <amodra@gmail.com>
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* elf/ppc64.h: Specify byte offset to local entry for values
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@ -204,7 +204,7 @@ extern const unsigned int spe2_num_opcodes;
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/* Opcode is only supported by Power8 architecture. */
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#define PPC_OPCODE_POWER8 0x1000000000ull
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/* Opcode is supported by ppc750cl. */
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/* Opcode is supported by ppc750cl/Gekko/Broadway. */
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#define PPC_OPCODE_750 0x2000000000ull
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/* Opcode is supported by ppc7450. */
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@ -1,3 +1,14 @@
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2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
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Alan Modra <amodra@gmail.com>
|
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|
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* ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
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(powerpc_init_dialect): Handle bfd_mach_ppc_750.
|
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* ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
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support disjointed BAT.
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(powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
|
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(XSPRGQR_MASK, GEKKO, BROADWAY): Define.
|
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(powerpc_opcodes): Add 750cl extended mnemonics for spr access.
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2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
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Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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@ -94,6 +94,10 @@ struct ppc_mopt ppc_opts[] = {
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0 },
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{ "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
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, 0 },
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{ "gekko", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
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, 0 },
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{ "broadway", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
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, 0 },
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{ "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
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0 },
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{ "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
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@ -313,6 +317,9 @@ powerpc_init_dialect (struct disassemble_info *info)
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case bfd_mach_ppc_601:
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dialect = ppc_parse_cpu (dialect, &sticky, "601");
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break;
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case bfd_mach_ppc_750:
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dialect = ppc_parse_cpu (dialect, &sticky, "750cl");
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break;
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case bfd_mach_ppc_a35:
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case bfd_mach_ppc_rs64ii:
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case bfd_mach_ppc_rs64iii:
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@ -1187,6 +1187,41 @@ extract_spr (uint64_t insn,
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return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
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}
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/* Some dialects have 8 [DI]BAT registers instead of the standard 4. */
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#define ALLOW8_BAT (PPC_OPCODE_750)
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static unsigned long
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insert_sprbat (unsigned long insn,
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long value,
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ppc_cpu_t dialect,
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const char **errmsg)
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{
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if (value > 7
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|| (value > 3 && (dialect & ALLOW8_BAT) == 0))
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*errmsg = _("invalid bat number");
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/* If this is [di]bat4..7 then use spr 560..575, otherwise 528..543. */
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if (value > 3)
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value = ((value & 3) << 6) | 1;
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else
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value = value << 6;
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return insn | (value << 11);
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}
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static long
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extract_sprbat (unsigned long insn,
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ppc_cpu_t dialect,
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int *invalid)
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{
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unsigned long val = (insn >> 17) & 0x3;
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val = val + ((insn >> 9) & 0x4);
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if (val > 3 && (dialect & ALLOW8_BAT) == 0)
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*invalid = 1;
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return val;
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}
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/* Some dialects have 8 SPRG registers instead of the standard 4. */
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#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
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@ -2305,11 +2340,16 @@ const struct powerpc_operand powerpc_operands[] =
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/* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
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#define SPRBAT SPR + 1
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#define SPRBAT_MASK (0x3 << 17)
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{ 0x3, 17, NULL, NULL, 0 },
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#define SPRBAT_MASK (0xc1 << 11)
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{ 0x7, PPC_OPSHIFT_INV, insert_sprbat, extract_sprbat, PPC_OPERAND_SPR },
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/* The GQR index number in an XFX form m[ft]gqr instruction. */
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#define SPRGQR SPRBAT + 1
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#define SPRGQR_MASK (0x7 << 16)
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{ 0x7, 16, NULL, NULL, PPC_OPERAND_GQR },
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/* The SPRG register number in an XFX form m[ft]sprg instruction. */
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#define SPRG SPRBAT + 1
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#define SPRG SPRGQR + 1
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{ 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR },
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/* The SR field in an X form instruction. */
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@ -3365,6 +3405,10 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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SPRBAT field. */
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#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
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/* An XFX form instruction with the SPR field filled in except for the
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SPRGQR field. */
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#define XSPRGQR_MASK (XSPR_MASK &~ SPRGQR_MASK)
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/* An XFX form instruction with the SPR field filled in except for the
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SPRG field. */
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#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
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@ -3480,6 +3524,8 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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#define PPC464 PPC440
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#define PPC476 PPC_OPCODE_476
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#define PPC750 PPC_OPCODE_750
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#define GEKKO PPC_OPCODE_750
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#define BROADWAY PPC_OPCODE_750
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#define PPC7450 PPC_OPCODE_7450
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#define PPC860 PPC_OPCODE_860
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#define PPCPS PPC_OPCODE_PPCPS
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@ -3512,7 +3558,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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#define PPCPMR PPC_OPCODE_PMR
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#define PPCTMR PPC_OPCODE_TMR
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#define PPCCHLK PPC_OPCODE_CACHELCK
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#define PPCRFMCI PPC_OPCODE_RFMCI
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#define PPCRFMCI PPC_OPCODE_RFMCI
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#define E500MC PPC_OPCODE_E500MC
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#define PPCA2 PPC_OPCODE_A2
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#define TITAN PPC_OPCODE_TITAN
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@ -5939,6 +5985,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
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{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
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{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
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{"mfgqr", XSPR(31,339,912), XSPRGQR_MASK, PPCPS, 0, {RT, SPRGQR}},
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{"mfhid2", XSPR(31,339,920), XSPR_MASK, GEKKO, 0, {RT}},
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{"mfwpar", XSPR(31,339,921), XSPR_MASK, GEKKO, 0, {RT}},
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{"mfdmau", XSPR(31,339,922), XSPR_MASK, GEKKO, 0, {RT}},
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{"mfdmal", XSPR(31,339,923), XSPR_MASK, GEKKO, 0, {RT}},
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{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
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{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
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{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
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@ -5983,10 +6034,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
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{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
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{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
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{"mfhid0", XSPR(31,339,1008), XSPR_MASK, GEKKO, 0, {RT}},
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{"mfhid1", XSPR(31,339,1009), XSPR_MASK, GEKKO, 0, {RT}},
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{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
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{"mfiabr", XSPR(31,339,1010), XSPR_MASK, GEKKO, 0, {RT}},
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{"mfhid4", XSPR(31,339,1011), XSPR_MASK, BROADWAY, 0, {RT}},
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{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
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{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
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{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
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{"mfdabr", XSPR(31,339,1013), XSPR_MASK, PPC750, 0, {RT}},
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{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
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{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
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{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
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@ -6269,6 +6325,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
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{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
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{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
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{"mtgqr", XSPR(31,467,912), XSPRGQR_MASK, PPCPS, 0, {SPRGQR, RS}},
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{"mthid2", XSPR(31,467,920), XSPR_MASK, GEKKO, 0, {RS}},
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{"mtwpar", XSPR(31,467,921), XSPR_MASK, GEKKO, 0, {RS}},
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{"mtdmau", XSPR(31,467,922), XSPR_MASK, GEKKO, 0, {RS}},
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{"mtdmal", XSPR(31,467,923), XSPR_MASK, GEKKO, 0, {RS}},
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{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
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{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
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{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
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@ -6309,10 +6370,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
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{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
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{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
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{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
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{"mthid0", XSPR(31,467,1008), XSPR_MASK, GEKKO, 0, {RS}},
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{"mthid1", XSPR(31,467,1009), XSPR_MASK, GEKKO, 0, {RS}},
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{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
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{"mtiabr", XSPR(31,467,1010), XSPR_MASK, GEKKO, 0, {RS}},
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{"mthid4", XSPR(31,467,1011), XSPR_MASK, BROADWAY, 0, {RS}},
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{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
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{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
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{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
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{"mtdabr", XSPR(31,467,1013), XSPR_MASK, PPC750, 0, {RS}},
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{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
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{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
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{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
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Reference in New Issue
Block a user