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sim: aarch64: use PRIx64 for formatting 64-bit types

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We can't assume that %lx is big enough for 64-bit types as it isn't on
most 32-bit builds.  Use the standard format define for this instead.
This commit is contained in:
Mike Frysinger
2021-05-01 15:54:33 -04:00
parent ce2248135a
commit f1ca32150c
2 changed files with 12 additions and 5 deletions
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6
sim/aarch64/ChangeLog
View File

@ -1,3 +1,9 @@
2021-05-01 Mike Frysinger <vapier@gentoo.org>
* cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
(aarch64_set_FP_double, aarch64_set_FP_long_double,
aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
2021-05-01 Mike Frysinger <vapier@gentoo.org>
* simulator.c (do_fcvtzu): Change UL to ULL.

11
sim/aarch64/cpustate.c
View File

@ -379,7 +379,7 @@ aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
v.s = val;
TRACE_REGISTER (cpu,
"FR[%d].s changes from %f to %f [hex: %0lx]",
"FR[%d].s changes from %f to %f [hex: %0" PRIx64 "]",
reg, cpu->fr[reg].s, val, v.v[0]);
}
@ -397,7 +397,7 @@ aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val)
v.d = val;
TRACE_REGISTER (cpu,
"FR[%d].d changes from %f to %f [hex: %0lx]",
"FR[%d].d changes from %f to %f [hex: %0" PRIx64 "]",
reg, cpu->fr[reg].d, val, v.v[0]);
}
cpu->fr[reg].d = val;
@ -409,7 +409,8 @@ aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a)
if (cpu->fr[reg].v[0] != a.v[0]
|| cpu->fr[reg].v[1] != a.v[1])
TRACE_REGISTER (cpu,
"FR[%d].q changes from [%0lx %0lx] to [%0lx %0lx] ",
"FR[%d].q changes from [%0" PRIx64 " %0" PRIx64 "] to [%0"
PRIx64 " %0" PRIx64 "] ",
reg,
cpu->fr[reg].v[0], cpu->fr[reg].v[1],
a.v[0], a.v[1]);
@ -518,7 +519,7 @@ aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element)
void
aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val)
{
SET_VEC_ELEMENT (reg, element, val, v, "%16lx");
SET_VEC_ELEMENT (reg, element, val, v, "%16" PRIx64);
}
void
@ -542,7 +543,7 @@ aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val)
void
aarch64_set_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element, int64_t val)
{
SET_VEC_ELEMENT (reg, element, val, V, "%16lx");
SET_VEC_ELEMENT (reg, element, val, V, "%16" PRIx64);
}
void