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https://github.com/espressif/binutils-gdb.git
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x86: optimize {,V}EXTRACT{F,I}{128,32x{4,8},64x{2,4}} with immediate 0
They, too, are equivalent to simple moves, which are up to 3 bytes shorter to encode (and maybe also cheaper to execute).
This commit is contained in:
Jan Beulich
@@ -5584,6 +5584,80 @@ optimize_encoding (void)
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i.reloc[1] = i.reloc[2];
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i.tm.operand_types[1] = i.tm.operand_types[2];
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i.operands = 2;
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i.imm_operands = 0;
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}
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else if ((i.tm.base_opcode | 0x22) == 0x3b
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&& i.tm.opcode_space == SPACE_0F3A
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&& i.op[0].imms->X_op == O_constant
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&& i.op[0].imms->X_add_number == 0)
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{
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/* Optimize: -O:
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vextractf128 $0, %ymmN, %xmmM -> vmovaps %xmmN, %xmmM
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vextractf128 $0, %ymmN, mem -> vmovups %xmmN, mem
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vextractf32x4 $0, %[yz]mmN, %xmmM -> vmovaps %xmmN, %xmmM
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vextractf32x4 $0, %[yz]mmN, mem -> vmovups %xmmN, mem
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vextractf64x2 $0, %[yz]mmN, %xmmM -> vmovapd %xmmN, %xmmM
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vextractf64x2 $0, %[yz]mmN, mem -> vmovupd %xmmN, mem
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vextractf32x8 $0, %zmmN, %ymmM -> vmovaps %ymmN, %ymmM
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vextractf32x8 $0, %zmmN, mem -> vmovups %ymmN, mem
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vextractf64x4 $0, %zmmN, %ymmM -> vmovapd %ymmN, %ymmM
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vextractf64x4 $0, %zmmN, mem -> vmovupd %ymmN, mem
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vextracti128 $0, %ymmN, %xmmM -> vmovdqa %xmmN, %xmmM
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vextracti128 $0, %ymmN, mem -> vmovdqu %xmmN, mem
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vextracti32x4 $0, %[yz]mmN, %xmmM -> vmovdqa{,32} %xmmN, %xmmM
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vextracti32x4 $0, %[yz]mmN, mem -> vmovdqu{,32} %xmmN, mem
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vextracti64x2 $0, %[yz]mmN, %xmmM -> vmovdqa{,64} %xmmN, %xmmM
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vextracti64x2 $0, %[yz]mmN, mem -> vmovdqu{,64} %xmmN, mem
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vextracti32x8 $0, %zmmN, %ymmM -> vmovdqa{,32} %ymmN, %ymmM
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vextracti32x8 $0, %zmmN, mem -> vmovdqu{,32} %ymmN, mem
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vextracti64x4 $0, %zmmN, %ymmM -> vmovdqa{,64} %ymmN, %ymmM
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vextracti64x4 $0, %zmmN, mem -> vmovdqu{,64} %ymmN, mem
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*/
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i.tm.opcode_space = SPACE_0F;
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if (!i.mask.reg
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&& (pp.encoding <= encoding_vex3
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|| (pp.encoding == encoding_evex512
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&& (!i.base_reg || !(i.base_reg->reg_flags & RegRex2))
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&& (!i.index_reg || !(i.index_reg->reg_flags & RegRex2)))))
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{
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i.tm.opcode_modifier.vex = i.tm.base_opcode & 2 ? VEX256 : VEX128;
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i.tm.opcode_modifier.evex = 0;
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}
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else
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i.tm.opcode_modifier.evex = i.tm.base_opcode & 2 ? EVEX256 : EVEX128;
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if (i.tm.base_opcode & 0x20)
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{
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i.tm.base_opcode = 0x7f;
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if (i.reg_operands != 2)
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i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
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}
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else
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{
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if (i.reg_operands == 2)
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i.tm.base_opcode = 0x29;
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else
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i.tm.base_opcode = 0x11;
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if (i.tm.opcode_modifier.vexw != VEXW1)
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i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE;
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}
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if (i.tm.opcode_modifier.vex)
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i.tm.opcode_modifier.vexw = VEXWIG;
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i.op[0].regs = i.op[1].regs;
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i.types[0] = i.types[1];
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i.flags[0] = i.flags[1];
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i.tm.operand_types[0] = i.tm.operand_types[1];
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i.op[1].regs = i.op[2].regs;
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i.types[1] = i.types[2];
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i.flags[1] = i.flags[2];
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i.reloc[1] = i.reloc[2];
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i.tm.operand_types[1] = i.tm.operand_types[2];
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i.operands = 2;
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i.imm_operands = 0;
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}
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@@ -170,6 +170,26 @@ Disassembly of section .text:
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+[a-f0-9]+: f3 .* movss %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovd %xmm1,%edx
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+[a-f0-9]+: c5 .* vmovss %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovups %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovups %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovapd %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovupd %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovups %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovdqu %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovapd %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovupd %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovdqu %ymm1,\(%edx\)
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+[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax
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+[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax
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+[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax
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@@ -199,6 +199,31 @@ _start:
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vextractps $0, %xmm1, %edx
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vextractps $0, %xmm1, (%edx)
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vextractf128 $0, %ymm1, %xmm2
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vextractf128 $0, %ymm1, (%edx)
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vextracti128 $0, %ymm1, %xmm2
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vextracti128 $0, %ymm1, (%edx)
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vextractf32x4 $0, %ymm1, %xmm2
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vextractf32x4 $0, %ymm1, (%edx)
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vextracti32x4 $0, %ymm1, %xmm2
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vextracti32x4 $0, %ymm1, (%edx)
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vextractf64x2 $0, %ymm1, %xmm2
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vextractf64x2 $0, %ymm1, (%edx)
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vextracti64x2 $0, %ymm1, %xmm2
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vextracti64x2 $0, %ymm1, (%edx)
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vextractf32x8 $0, %zmm1, %ymm2
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vextractf32x8 $0, %zmm1, (%edx)
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vextracti32x8 $0, %zmm1, %ymm2
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vextracti32x8 $0, %zmm1, (%edx)
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vextractf64x4 $0, %zmm1, %ymm2
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vextractf64x4 $0, %zmm1, (%edx)
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vextracti64x4 $0, %zmm1, %ymm2
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vextracti64x4 $0, %zmm1, (%edx)
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bt $15, %ax
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bt $16, %ax
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btc $15, %ax
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@@ -171,6 +171,26 @@ Disassembly of section .text:
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+[a-f0-9]+: f3 .* movss %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovd %xmm1,%edx
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+[a-f0-9]+: c5 .* vmovss %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovups %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovups %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovapd %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovupd %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovups %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovdqu %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovapd %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovupd %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovdqu %ymm1,\(%edx\)
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+[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax
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+[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax
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+[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax
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@@ -170,6 +170,26 @@ Disassembly of section .text:
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+[a-f0-9]+: f3 .* movss %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovd %xmm1,%edx
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+[a-f0-9]+: c5 .* vmovss %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovups %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovups %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovapd %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovupd %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovups %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovdqu %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovapd %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovupd %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovdqu %ymm1,\(%edx\)
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+[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax
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+[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax
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+[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax
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@@ -170,6 +170,26 @@ Disassembly of section .text:
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+[a-f0-9]+: f3 .* movss %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovd %xmm1,%edx
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+[a-f0-9]+: c5 .* vmovss %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovups %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovups %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovapd %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovupd %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 .* vmovdqu %xmm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovaps %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovups %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovdqu %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovapd %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovupd %ymm1,\(%edx\)
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+[a-f0-9]+: c5 .* vmovdqa %ymm1,%ymm2
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+[a-f0-9]+: c5 .* vmovdqu %ymm1,\(%edx\)
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+[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax
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+[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax
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+[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax
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59
gas/testsuite/gas/i386/x86-64-optimize-vextractNN.d
Normal file
59
gas/testsuite/gas/i386/x86-64-optimize-vextractNN.d
Normal file
@@ -0,0 +1,59 @@
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#as: -O
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#objdump: -drw
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#name: x86-64 VEXTRACT{F,I}<nn> optimized encoding with -msse2avx
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.*: +file format .*
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Disassembly of section .text:
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0+ <vextract_128>:
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+[a-f0-9]+: c5 f8 29 ca vmovaps %xmm1,%xmm2
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+[a-f0-9]+: c5 f8 11 0a vmovups %xmm1,\(%rdx\)
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+[a-f0-9]+: c5 f9 7f ca vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 fa 7f 0a vmovdqu %xmm1,\(%rdx\)
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0+[a-f0-9]+ <vextract_NNxM_XMM>:
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+[a-f0-9]+: c5 f8 29 ca vmovaps %xmm1,%xmm2
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+[a-f0-9]+: c5 f8 11 0a vmovups %xmm1,\(%rdx\)
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+[a-f0-9]+: 62 e1 7c 08 29 ca vmovaps %xmm17,%xmm2
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+[a-f0-9]+: 62 e1 7c 08 11 0a vmovups %xmm17,\(%rdx\)
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+[a-f0-9]+: 62 f9 7c 08 11 0a vmovups %xmm1,\(%r18\)
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+[a-f0-9]+: c5 f9 29 ca vmovapd %xmm1,%xmm2
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+[a-f0-9]+: c5 f9 11 0a vmovupd %xmm1,\(%rdx\)
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+[a-f0-9]+: 62 e1 fd 08 29 ca vmovapd %xmm17,%xmm2
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+[a-f0-9]+: 62 e1 fd 08 11 0a vmovupd %xmm17,\(%rdx\)
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+[a-f0-9]+: 62 f9 fd 08 11 0a vmovupd %xmm1,\(%r18\)
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+[a-f0-9]+: c5 f9 7f ca vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 fa 7f 0a vmovdqu %xmm1,\(%rdx\)
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+[a-f0-9]+: 62 e1 7d 08 7f ca vmovdqa32 %xmm17,%xmm2
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+[a-f0-9]+: 62 e1 7e 08 7f 0a vmovdqu32 %xmm17,\(%rdx\)
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+[a-f0-9]+: 62 f9 7e 08 7f 0a vmovdqu32 %xmm1,\(%r18\)
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+[a-f0-9]+: c5 f9 7f ca vmovdqa %xmm1,%xmm2
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+[a-f0-9]+: c5 fa 7f 0a vmovdqu %xmm1,\(%rdx\)
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+[a-f0-9]+: 62 e1 fd 08 7f ca vmovdqa64 %xmm17,%xmm2
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+[a-f0-9]+: 62 e1 fe 08 7f 0a vmovdqu64 %xmm17,\(%rdx\)
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+[a-f0-9]+: 62 f9 fe 08 7f 0a vmovdqu64 %xmm1,\(%r18\)
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0+[a-f0-9]+ <vextract_NNxM_YMM>:
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+[a-f0-9]+: c5 fc 29 ca vmovaps %ymm1,%ymm2
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+[a-f0-9]+: c5 fc 11 0a vmovups %ymm1,\(%rdx\)
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+[a-f0-9]+: 62 e1 7c 28 29 ca vmovaps %ymm17,%ymm2
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+[a-f0-9]+: 62 e1 7c 28 11 0a vmovups %ymm17,\(%rdx\)
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+[a-f0-9]+: 62 f9 7c 28 11 0a vmovups %ymm1,\(%r18\)
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+[a-f0-9]+: c5 fd 29 ca vmovapd %ymm1,%ymm2
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+[a-f0-9]+: c5 fd 11 0a vmovupd %ymm1,\(%rdx\)
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+[a-f0-9]+: 62 e1 fd 28 29 ca vmovapd %ymm17,%ymm2
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+[a-f0-9]+: 62 e1 fd 28 11 0a vmovupd %ymm17,\(%rdx\)
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+[a-f0-9]+: 62 f9 fd 28 11 0a vmovupd %ymm1,\(%r18\)
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+[a-f0-9]+: c5 fd 7f ca vmovdqa %ymm1,%ymm2
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+[a-f0-9]+: c5 fe 7f 0a vmovdqu %ymm1,\(%rdx\)
|
||||
+[a-f0-9]+: 62 e1 7d 28 7f ca vmovdqa32 %ymm17,%ymm2
|
||||
+[a-f0-9]+: 62 e1 7e 28 7f 0a vmovdqu32 %ymm17,\(%rdx\)
|
||||
+[a-f0-9]+: 62 f9 7e 28 7f 0a vmovdqu32 %ymm1,\(%r18\)
|
||||
+[a-f0-9]+: c5 fd 7f ca vmovdqa %ymm1,%ymm2
|
||||
+[a-f0-9]+: c5 fe 7f 0a vmovdqu %ymm1,\(%rdx\)
|
||||
+[a-f0-9]+: 62 e1 fd 28 7f ca vmovdqa64 %ymm17,%ymm2
|
||||
+[a-f0-9]+: 62 e1 fe 28 7f 0a vmovdqu64 %ymm17,\(%rdx\)
|
||||
+[a-f0-9]+: 62 f9 fe 28 7f 0a vmovdqu64 %ymm1,\(%r18\)
|
||||
#pass
|
||||
57
gas/testsuite/gas/i386/x86-64-optimize-vextractNN.s
Normal file
57
gas/testsuite/gas/i386/x86-64-optimize-vextractNN.s
Normal file
@@ -0,0 +1,57 @@
|
||||
.text
|
||||
vextract_128:
|
||||
vextractf128 $0, %ymm1, %xmm2
|
||||
vextractf128 $0, %ymm1, (%rdx)
|
||||
|
||||
vextracti128 $0, %ymm1, %xmm2
|
||||
vextracti128 $0, %ymm1, (%rdx)
|
||||
|
||||
vextract_NNxM_XMM:
|
||||
vextractf32x4 $0, %ymm1, %xmm2
|
||||
vextractf32x4 $0, %ymm1, (%rdx)
|
||||
vextractf32x4 $0, %ymm17, %xmm2
|
||||
vextractf32x4 $0, %ymm17, (%rdx)
|
||||
vextractf32x4 $0, %ymm1, (%r18)
|
||||
|
||||
vextractf64x2 $0, %ymm1, %xmm2
|
||||
vextractf64x2 $0, %ymm1, (%rdx)
|
||||
vextractf64x2 $0, %ymm17, %xmm2
|
||||
vextractf64x2 $0, %ymm17, (%rdx)
|
||||
vextractf64x2 $0, %ymm1, (%r18)
|
||||
|
||||
vextracti32x4 $0, %ymm1, %xmm2
|
||||
vextracti32x4 $0, %ymm1, (%rdx)
|
||||
vextracti32x4 $0, %ymm17, %xmm2
|
||||
vextracti32x4 $0, %ymm17, (%rdx)
|
||||
vextracti32x4 $0, %ymm1, (%r18)
|
||||
|
||||
vextracti64x2 $0, %ymm1, %xmm2
|
||||
vextracti64x2 $0, %ymm1, (%rdx)
|
||||
vextracti64x2 $0, %ymm17, %xmm2
|
||||
vextracti64x2 $0, %ymm17, (%rdx)
|
||||
vextracti64x2 $0, %ymm1, (%r18)
|
||||
|
||||
vextract_NNxM_YMM:
|
||||
vextractf32x8 $0, %zmm1, %ymm2
|
||||
vextractf32x8 $0, %zmm1, (%rdx)
|
||||
vextractf32x8 $0, %zmm17, %ymm2
|
||||
vextractf32x8 $0, %zmm17, (%rdx)
|
||||
vextractf32x8 $0, %zmm1, (%r18)
|
||||
|
||||
vextractf64x4 $0, %zmm1, %ymm2
|
||||
vextractf64x4 $0, %zmm1, (%rdx)
|
||||
vextractf64x4 $0, %zmm17, %ymm2
|
||||
vextractf64x4 $0, %zmm17, (%rdx)
|
||||
vextractf64x4 $0, %zmm1, (%r18)
|
||||
|
||||
vextracti32x8 $0, %zmm1, %ymm2
|
||||
vextracti32x8 $0, %zmm1, (%rdx)
|
||||
vextracti32x8 $0, %zmm17, %ymm2
|
||||
vextracti32x8 $0, %zmm17, (%rdx)
|
||||
vextracti32x8 $0, %zmm1, (%r18)
|
||||
|
||||
vextracti64x4 $0, %zmm1, %ymm2
|
||||
vextracti64x4 $0, %zmm1, (%rdx)
|
||||
vextracti64x4 $0, %zmm17, %ymm2
|
||||
vextracti64x4 $0, %zmm17, (%rdx)
|
||||
vextracti64x4 $0, %zmm1, (%r18)
|
||||
@@ -596,6 +596,7 @@ run_list_test "x86-64-optimize-pextr" "-O -aln"
|
||||
run_dump_test "x86-64-optimize-pextr"
|
||||
run_list_test "x86-64-optimize-extractps" "-O -aln"
|
||||
run_dump_test "x86-64-optimize-extractps"
|
||||
run_dump_test "x86-64-optimize-vextractNN"
|
||||
run_dump_test "x86-64-apx-ndd-optimize"
|
||||
run_dump_test "x86-64-align-branch-1a"
|
||||
run_dump_test "x86-64-align-branch-1b"
|
||||
|
||||
@@ -1664,7 +1664,7 @@ vcvttps2dq, 0xf35b, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex
|
||||
vcvtts<sd>2si, 0x<sd:spfx>2c, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
|
||||
vdppd, 0x6641, AVX, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vdpps, 0x6640, AVX, Modrm|Vex|Space0F3A|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vextractf128, 0x6619, AVX, Modrm|Vex256|Space0F3A|VexW0|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
|
||||
vextractf128, 0x6619, AVX, Modrm|Vex256|Space0F3A|VexW0|NoSuf|Optimize, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
|
||||
vextractps, 0x6617, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf|Optimize, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex }
|
||||
vextractps, 0x6617, x64&(AVX|AVX512F), RegMem|Vex128|EVex128|Space0F3A|VexWIG|NoSuf|Optimize, { Imm8, RegXMM, Reg64 }
|
||||
vhaddpd, 0x667c, AVX, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
@@ -1864,7 +1864,7 @@ vpermd, 0x6636, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F38|Src1VVVV|Ve
|
||||
vpermpd, 0x6601, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
|
||||
vpermps, 0x6616, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
|
||||
vpermq, 0x6600, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
|
||||
vextracti128, 0x6639, AVX2, Modrm|Vex256|Space0F3A|VexW0|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
|
||||
vextracti128, 0x6639, AVX2, Modrm|Vex256|Space0F3A|VexW0|NoSuf|Optimize, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
|
||||
vinserti128, 0x6638, AVX2, Modrm|Vex256|Space0F3A|Src1VVVV|VexW0|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
|
||||
vpmaskmov<dq>, 0x668e, AVX2, Modrm|Vex|Space0F38|Src1VVVV|<dq:vexw>|CheckOperandSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
|
||||
vpmaskmov<dq>, 0x668c, AVX2, Modrm|Vex|Space0F38|Src1VVVV|<dq:vexw>|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
@@ -2356,11 +2356,11 @@ vpexpandq, 0x6689, AVX512F, Modrm|Masking|Space0F38|VexW=2|Disp8MemShift=3|Check
|
||||
vexpandps, 0x6688, AVX512F, Modrm|Masking|Space0F38|VexW=1|Disp8MemShift=2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
|
||||
vpexpandd, 0x6689, AVX512F, Modrm|Masking|Space0F38|VexW=1|Disp8MemShift=2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
|
||||
|
||||
vextractf32x4, 0x6619, AVX512F, Modrm|Masking|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
|
||||
vextracti32x4, 0x6639, AVX512F, Modrm|Masking|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
|
||||
vextractf32x4, 0x6619, AVX512F, Modrm|Masking|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf|Optimize, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
|
||||
vextracti32x4, 0x6639, AVX512F, Modrm|Masking|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf|Optimize, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
|
||||
|
||||
vextractf64x4, 0x661B, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
|
||||
vextracti64x4, 0x663B, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
|
||||
vextractf64x4, 0x661B, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf|Optimize, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
|
||||
vextracti64x4, 0x663B, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf|Optimize, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
|
||||
|
||||
vfixupimmp<sd>, 0x6654, AVX512F, Modrm|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
|
||||
vfixupimms<sd>, 0x6655, AVX512F, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8|Imm8S, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
@@ -2814,16 +2814,16 @@ vcvttps2uqq, 0x6678, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broa
|
||||
|
||||
vcvtuqq2ps<Exy>, 0xf27a, AVX512DQ&<Exy:vl>, Modrm|<Exy:attr>|Masking|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> }
|
||||
|
||||
vextractf32x8, 0x661B, AVX512DQ, Modrm|EVex=1|Masking|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
|
||||
vextracti32x8, 0x663B, AVX512DQ, Modrm|EVex=1|Masking|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
|
||||
vextractf32x8, 0x661B, AVX512DQ, Modrm|EVex=1|Masking|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf|Optimize, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
|
||||
vextracti32x8, 0x663B, AVX512DQ, Modrm|EVex=1|Masking|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf|Optimize, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
|
||||
vinsertf32x8, 0x661A, AVX512DQ, Modrm|EVex512|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vinserti32x8, 0x663A, AVX512DQ, Modrm|EVex512|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
|
||||
vpextr<dq>, 0x6616, AVX512DQ&<dq:cpu64>, Modrm|EVex128|Space0F3A|<dq:vexw64>|Disp8MemShift|NoSuf|Optimize, { Imm8, RegXMM, <dq:gpr>|Unspecified|BaseIndex }
|
||||
vpinsr<dq>, 0x6622, AVX512DQ&<dq:cpu64>, Modrm|EVex128|Space0F3A|Src1VVVV|<dq:vexw64>|Disp8MemShift|NoSuf, { Imm8, <dq:gpr>|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
|
||||
vextractf64x2, 0x6619, AVX512DQ, Modrm|Masking|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
|
||||
vextracti64x2, 0x6639, AVX512DQ, Modrm|Masking|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
|
||||
vextractf64x2, 0x6619, AVX512DQ, Modrm|Masking|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf|Optimize, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
|
||||
vextracti64x2, 0x6639, AVX512DQ, Modrm|Masking|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf|Optimize, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
|
||||
vinsertf64x2, 0x6618, AVX512DQ, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
|
||||
vinserti64x2, 0x6638, AVX512DQ, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
|
||||
|
||||
|
||||
@@ -25952,7 +25952,7 @@ static const insn_template i386_optab[] =
|
||||
1, 1, 0, 0, 0, 0 } } } },
|
||||
{ MN_vextractf128, 0x19, 3, SPACE_0F3A, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
|
||||
0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@@ -30722,7 +30722,7 @@ static const insn_template i386_optab[] =
|
||||
0, 1, 1, 0, 0, 0 } } } },
|
||||
{ MN_vextracti128, 0x39, 3, SPACE_0F3A, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 2, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
|
||||
0, 0 },
|
||||
{ { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@@ -37370,7 +37370,7 @@ static const insn_template i386_optab[] =
|
||||
1, 1, 1, 0, 0, 0 } } } },
|
||||
{ MN_vextractf32x4, 0x19, 3, SPACE_0F3A, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 5, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 5, 1, 0, 0, 0, 4, 1, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@@ -37382,7 +37382,7 @@ static const insn_template i386_optab[] =
|
||||
1, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_vextracti32x4, 0x39, 3, SPACE_0F3A, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 5, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 5, 1, 0, 0, 0, 4, 1, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@@ -37394,7 +37394,7 @@ static const insn_template i386_optab[] =
|
||||
1, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_vextractf64x4, 0x1b, 3, SPACE_0F3A, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 2, 1, 0, 0, 1, 1, 0, 0, 0, 5, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 2, 1, 0, 0, 1, 1, 0, 0, 0, 5, 1, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@@ -37406,7 +37406,7 @@ static const insn_template i386_optab[] =
|
||||
0, 1, 0, 0, 1, 0 } } } },
|
||||
{ MN_vextracti64x4, 0x3b, 3, SPACE_0F3A, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 2, 1, 0, 0, 1, 1, 0, 0, 0, 5, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 2, 1, 0, 0, 1, 1, 0, 0, 0, 5, 1, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@@ -40794,7 +40794,7 @@ static const insn_template i386_optab[] =
|
||||
1, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_vextractf32x8, 0x1b, 3, SPACE_0F3A, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 5, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 5, 1, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@@ -40806,7 +40806,7 @@ static const insn_template i386_optab[] =
|
||||
0, 1, 0, 0, 1, 0 } } } },
|
||||
{ MN_vextracti32x8, 0x3b, 3, SPACE_0F3A, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 5, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 5, 1, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@@ -40846,7 +40846,7 @@ static const insn_template i386_optab[] =
|
||||
0, 0, 1, 0, 0, 0 } } } },
|
||||
{ MN_vextractf64x2, 0x19, 3, SPACE_0F3A, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 1, 0, 0, 0, 4, 1, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@@ -40858,7 +40858,7 @@ static const insn_template i386_optab[] =
|
||||
1, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_vextracti64x2, 0x39, 3, SPACE_0F3A, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 1, 0, 0, 0, 4, 1, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
|
||||
Reference in New Issue
Block a user