aarch64: fix incorrect encoding for system register pmsdsfr_el1

This patch fixes a mistake in the encoding of the system register
pmsdsfr_el1.

Reference:
https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/PMSDSFR-EL1--Sampling-Data-Source-Filter-Register?lang=en
This commit is contained in:
Matthieu Longo
2024-05-17 12:04:25 +01:00
committed by Richard Earnshaw
parent bbe8d019ed
commit ef2d28fd02
2 changed files with 3 additions and 3 deletions

View File

@@ -7,8 +7,8 @@
Disassembly of section \.text:
0+ <.*>:
.*: d51c9a83 msr pmsdsfr_el1, x3
.*: d53c9a83 mrs x3, pmsdsfr_el1
.*: d5189a83 msr pmsdsfr_el1, x3
.*: d5389a83 mrs x3, pmsdsfr_el1
.*: d5385340 mrs x0, erxgsr_el1
.*: d5181063 msr sctlr2_el1, x3
.*: d5381063 mrs x3, sctlr2_el1

View File

@@ -741,7 +741,7 @@
SYSREG ("pmscr_el1", CPENC (3,0,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmscr_el12", CPENC (3,5,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmscr_el2", CPENC (3,4,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmsdsfr_el1", CPENC (3,4,9,10,4), F_ARCHEXT, AARCH64_FEATURE (SPE_FDS))
SYSREG ("pmsdsfr_el1", CPENC (3,0,9,10,4), F_ARCHEXT, AARCH64_FEATURE (SPE_FDS))
SYSREG ("pmselr_el0", CPENC (3,3,9,12,5), 0, AARCH64_NO_FEATURES)
SYSREG ("pmsevfr_el1", CPENC (3,0,9,9,5), F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmsfcr_el1", CPENC (3,0,9,9,4), F_ARCHEXT, AARCH64_FEATURE (PROFILE))