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x86/Intel: don't swap operands of MONITOR{,X} and MWAIT{,X}
Generally, the documentation doesn't allow for any explicit operands to be specified with MONITOR/MWAIT. To permit the more legible overriding of the address size via specifying operands, the option is being retained even in Intel mode, but operand swapping is being suppressed by this patch. This is both because it makes no sense here (all of the operands are inputs) and because, as a result, old gcc (prior to 4.8) actually expects it this way with -mintel-syntax (and hence gets fixed by this change rather than, as claimed by a reply in the bug report, broken).
This commit is contained in:
Jan Beulich
@ -1,3 +1,16 @@
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2020-02-17 Jan Beulich <jbeulich@suse.com>
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PR gas/14439
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* config/tc-i386.c (md_assemble): Also suppress operand
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swapping for MONITOR{,X} and MWAIT{,X}.
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* testsuite/gas/i386/sse3.s, testsuite/gas/i386/x86-64-sse3.s:
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Add Intel syntax monitor/mwait tests.
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* testsuite/gas/i386/sse3.d, testsuite/gas/i386/x86-64-sse3.d:
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Adjust expectations.
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*testsuite/gas/i386/sse3-intel.d,
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testsuite/gas/i386/x86-64-sse3-intel.d: New.
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* testsuite/gas/i386/i386.exp: Run new tests.
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2020-02-17 Jan Beulich <jbeulich@suse.com>
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PR gas/6518
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@ -4324,14 +4324,16 @@ md_assemble (char *line)
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/* Now we've parsed the mnemonic into a set of templates, and have the
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operands at hand. */
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/* All intel opcodes have reversed operands except for "bound" and
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"enter". We also don't reverse intersegment "jmp" and "call"
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instructions with 2 immediate operands so that the immediate segment
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precedes the offset, as it does when in AT&T mode. */
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/* All Intel opcodes have reversed operands except for "bound", "enter"
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"monitor*", and "mwait*". We also don't reverse intersegment "jmp"
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and "call" instructions with 2 immediate operands so that the immediate
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segment precedes the offset, as it does when in AT&T mode. */
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if (intel_syntax
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&& i.operands > 1
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&& (strcmp (mnemonic, "bound") != 0)
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&& (strcmp (mnemonic, "invlpga") != 0)
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&& (strncmp (mnemonic, "monitor", 7) != 0)
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&& (strncmp (mnemonic, "mwait", 5) != 0)
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&& !(operand_type_check (i.types[0], imm)
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&& operand_type_check (i.types[1], imm)))
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swap_operands ();
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@ -77,6 +77,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "sse2-16bit"
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run_dump_test "sub"
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run_dump_test "sse3"
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run_dump_test "sse3-intel"
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run_dump_test "sib"
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run_dump_test "sib-intel"
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run_dump_test "disp"
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@ -700,6 +701,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-vmfunc"
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run_dump_test "immed64"
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run_dump_test "x86-64-sse3"
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run_dump_test "x86-64-sse3-intel"
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run_dump_test "x86-64-crx"
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run_dump_test "x86-64-crx-suffix"
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run_dump_test "x86-64-drx"
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43
gas/testsuite/gas/i386/sse3-intel.d
Normal file
43
gas/testsuite/gas/i386/sse3-intel.d
Normal file
@ -0,0 +1,43 @@
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#objdump: -dwMintel
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#name: i386 SSE3 (Intel disassembly)
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#source: sse3.s
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.*: +file format .*
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Disassembly of section .text:
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0+000 <foo>:
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[ ]*[0-9a-f]+: 66 0f d0 01[ ]+addsubpd xmm0,(XMMWORD PTR )?\[ecx\]
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[ ]*[0-9a-f]+: 66 0f d0 ca[ ]+addsubpd xmm1,xmm2
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[ ]*[0-9a-f]+: f2 0f d0 13[ ]+addsubps xmm2,(XMMWORD PTR )?\[ebx\]
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[ ]*[0-9a-f]+: f2 0f d0 dc[ ]+addsubps xmm3,xmm4
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[ ]*[0-9a-f]+: df 88 90 90 90 90[ ]+fisttp WORD PTR \[eax-0x6f6f6f70\]
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[ ]*[0-9a-f]+: db 88 90 90 90 90[ ]+fisttp DWORD PTR \[eax-0x6f6f6f70\]
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[ ]*[0-9a-f]+: dd 88 90 90 90 90[ ]+fisttp QWORD PTR \[eax-0x6f6f6f70\]
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[ ]*[0-9a-f]+: 66 0f 7c 65 00[ ]+haddpd xmm4,(XMMWORD PTR )?\[ebp(\+0x0)\]
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[ ]*[0-9a-f]+: 66 0f 7c ee[ ]+haddpd xmm5,xmm6
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[ ]*[0-9a-f]+: f2 0f 7c 37[ ]+haddps xmm6,(XMMWORD PTR )?\[edi\]
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[ ]*[0-9a-f]+: f2 0f 7c f8[ ]+haddps xmm7,xmm0
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[ ]*[0-9a-f]+: 66 0f 7d c1[ ]+hsubpd xmm0,xmm1
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[ ]*[0-9a-f]+: 66 0f 7d 0a[ ]+hsubpd xmm1,(XMMWORD PTR )?\[edx\]
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[ ]*[0-9a-f]+: f2 0f 7d d2[ ]+hsubps xmm2,xmm2
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[ ]*[0-9a-f]+: f2 0f 7d 1c 24[ ]+hsubps xmm3,(XMMWORD PTR )?\[esp\]
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[ ]*[0-9a-f]+: f2 0f f0 2e[ ]+lddqu xmm5,(XMMWORD PTR )?\[esi\]
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[ ]*[0-9a-f]+: 0f 01 c8[ ]+monitor *
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[ ]*[0-9a-f]+: 0f 01 c8[ ]+monitor *
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[ ]*[0-9a-f]+: f2 0f 12 f7[ ]+movddup xmm6,xmm7
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[ ]*[0-9a-f]+: f2 0f 12 38[ ]+movddup xmm7,(QWORD PTR )?\[eax\]
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[ ]*[0-9a-f]+: f3 0f 16 01[ ]+movshdup xmm0,(XMMWORD PTR )?\[ecx\]
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[ ]*[0-9a-f]+: f3 0f 16 ca[ ]+movshdup xmm1,xmm2
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[ ]*[0-9a-f]+: f3 0f 12 13[ ]+movsldup xmm2,(XMMWORD PTR )?\[ebx\]
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[ ]*[0-9a-f]+: f3 0f 12 dc[ ]+movsldup xmm3,xmm4
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[ ]*[0-9a-f]+: 0f 01 c9[ ]+mwait *
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[ ]*[0-9a-f]+: 0f 01 c9[ ]+mwait *
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[ ]*[0-9a-f]+: 67 0f 01 c8[ ]+addr16 monitor *
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[ ]*[0-9a-f]+: 67 0f 01 c8[ ]+addr16 monitor *
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[ ]*[0-9a-f]+: f2 0f 12 38[ ]+movddup xmm7,(QWORD PTR )?\[eax\]
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[ ]*[0-9a-f]+: f2 0f 12 38[ ]+movddup xmm7,(QWORD PTR )?\[eax\]
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[ ]*[0-9a-f]+: 0f 01 c8[ ]+monitor *
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[ ]*[0-9a-f]+: 67 0f 01 c8[ ]+addr16 monitor *
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[ ]*[0-9a-f]+: 0f 01 c9[ ]+mwait *
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#pass
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@ -36,4 +36,7 @@ Disassembly of section .text:
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70: 67 0f 01 c8 [ ]*monitor %ax,%ecx,%edx
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74: f2 0f 12 38 [ ]*movddup \(%eax\),%xmm7
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78: f2 0f 12 38 [ ]*movddup \(%eax\),%xmm7
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[ ]*[0-9a-f]+: 0f 01 c8[ ]+monitor %eax,%ecx,%edx
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[ ]*[0-9a-f]+: 67 0f 01 c8[ ]+monitor %ax,%ecx,%edx
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[ ]*[0-9a-f]+: 0f 01 c9[ ]+mwait %eax,%ecx
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#pass
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@ -35,3 +35,7 @@ foo:
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.intel_syntax noprefix
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movddup xmm7,[eax]
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movddup xmm7,QWORD PTR [eax]
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monitor eax, ecx, edx
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monitor ax, ecx, edx
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mwait eax, ecx
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46
gas/testsuite/gas/i386/x86-64-sse3-intel.d
Normal file
46
gas/testsuite/gas/i386/x86-64-sse3-intel.d
Normal file
@ -0,0 +1,46 @@
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#objdump: -dwMintel
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#name: x86-64 SSE3 (Intel disassembly)
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#source: x86-64-sse3.s
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.*: +file format .*
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Disassembly of section .text:
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0+000 <foo>:
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[ ]*[a-f0-9]+: 66 0f d0 01[ ]+addsubpd xmm0,(XMMWORD PTR )?\[rcx\]
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[ ]*[a-f0-9]+: 66 0f d0 ca[ ]+addsubpd xmm1,xmm2
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[ ]*[a-f0-9]+: f2 0f d0 13[ ]+addsubps xmm2,(XMMWORD PTR )?\[rbx\]
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[ ]*[a-f0-9]+: f2 0f d0 dc[ ]+addsubps xmm3,xmm4
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[ ]*[a-f0-9]+: df 88 90 90 90 00[ ]+fisttp WORD PTR \[rax\+0x909090\]
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[ ]*[a-f0-9]+: db 88 90 90 90 00[ ]+fisttp DWORD PTR \[rax\+0x909090\]
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[ ]*[a-f0-9]+: dd 88 90 90 90 00[ ]+fisttp QWORD PTR \[rax\+0x909090\]
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[ ]*[a-f0-9]+: 66 0f 7c 65 00[ ]+haddpd xmm4,(XMMWORD PTR )?\[rbp(\+0x0)\]
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[ ]*[a-f0-9]+: 66 0f 7c ee[ ]+haddpd xmm5,xmm6
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[ ]*[a-f0-9]+: f2 0f 7c 37[ ]+haddps xmm6,(XMMWORD PTR )?\[rdi\]
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[ ]*[a-f0-9]+: f2 0f 7c f8[ ]+haddps xmm7,xmm0
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[ ]*[a-f0-9]+: 66 0f 7d c1[ ]+hsubpd xmm0,xmm1
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[ ]*[a-f0-9]+: 66 0f 7d 0a[ ]+hsubpd xmm1,(XMMWORD PTR )?\[rdx\]
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[ ]*[a-f0-9]+: f2 0f 7d d2[ ]+hsubps xmm2,xmm2
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[ ]*[a-f0-9]+: f2 0f 7d 1c 24[ ]+hsubps xmm3,(XMMWORD PTR )?\[rsp\]
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[ ]*[a-f0-9]+: f2 0f f0 2e[ ]+lddqu xmm5,(XMMWORD PTR )?\[rsi\]
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[ ]*[a-f0-9]+: 0f 01 c8[ ]+monitor *
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[ ]*[a-f0-9]+: 0f 01 c8[ ]+monitor *
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[ ]*[a-f0-9]+: 0f 01 c8[ ]+monitor *
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[ ]*[a-f0-9]+: f2 0f 12 f7[ ]+movddup xmm6,xmm7
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[ ]*[a-f0-9]+: f2 0f 12 38[ ]+movddup xmm7,(QWORD PTR )?\[rax\]
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[ ]*[a-f0-9]+: f3 0f 16 01[ ]+movshdup xmm0,(XMMWORD PTR )?\[rcx\]
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[ ]*[a-f0-9]+: f3 0f 16 ca[ ]+movshdup xmm1,xmm2
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[ ]*[a-f0-9]+: f3 0f 12 13[ ]+movsldup xmm2,(XMMWORD PTR )?\[rbx\]
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[ ]*[a-f0-9]+: f3 0f 12 dc[ ]+movsldup xmm3,xmm4
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[ ]*[a-f0-9]+: 0f 01 c9[ ]+mwait *
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[ ]*[a-f0-9]+: 0f 01 c9[ ]+mwait *
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[ ]*[a-f0-9]+: 0f 01 c9[ ]+mwait *
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[ ]*[a-f0-9]+: 67 0f 01 c8[ ]+addr32 monitor *
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[ ]*[a-f0-9]+: 67 0f 01 c8[ ]+addr32 monitor *
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[ ]*[a-f0-9]+: 67 0f 01 c8[ ]+addr32 monitor *
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[ ]*[a-f0-9]+: f2 0f 12 38[ ]+movddup xmm7,(QWORD PTR )?\[rax\]
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[ ]*[a-f0-9]+: f2 0f 12 38[ ]+movddup xmm7,(QWORD PTR )?\[rax\]
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[ ]*[a-f0-9]+: 0f 01 c8[ ]+monitor *
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[ ]*[a-f0-9]+: 67 0f 01 c8[ ]+addr32 monitor *
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[ ]*[a-f0-9]+: 0f 01 c9[ ]+mwait *
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#pass
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@ -39,4 +39,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 0f 01 c8 [ ]*monitor %eax,%ecx,%edx
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[ ]*[a-f0-9]+: f2 0f 12 38 [ ]*movddup \(%rax\),%xmm7
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[ ]*[a-f0-9]+: f2 0f 12 38 [ ]*movddup \(%rax\),%xmm7
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[ ]*[0-9a-f]+: 0f 01 c8[ ]+monitor %rax,%ecx,%edx
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[ ]*[0-9a-f]+: 67 0f 01 c8[ ]+monitor %eax,%ecx,%edx
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[ ]*[0-9a-f]+: 0f 01 c9[ ]+mwait %eax,%ecx
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#pass
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@ -38,3 +38,7 @@ foo:
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.intel_syntax noprefix
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movddup xmm7,[rax]
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movddup xmm7,QWORD PTR [rax]
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monitor rax, ecx, edx
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monitor eax, ecx, edx
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mwait eax, ecx
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