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gdb: Support stepping out from signal handler on riscv*-linux
Currently, gdb cannot step outside of a signal handler on RISC-V platforms. This causes multiple failures in gdb.base/sigstep.exp: FAIL: gdb.base/sigstep.exp: continue to handler, nothing in handler, step from handler: leave handler (timeout) FAIL: gdb.base/sigstep.exp: continue to handler, si+advance in handler, step from handler: leave handler (timeout) FAIL: gdb.base/sigstep.exp: continue to handler, nothing in handler, next from handler: leave handler (timeout) FAIL: gdb.base/sigstep.exp: continue to handler, si+advance in handler, next from handler: leave handler (timeout) FAIL: gdb.base/sigstep.exp: stepi from handleri: leave signal trampoline FAIL: gdb.base/sigstep.exp: nexti from handleri: leave signal trampoline === gdb Summary === # of expected passes 587 # of unexpected failures 6 This patch adds support for stepping outside of a signal handler on riscv*-*-linux*. Implementation is heavily inspired from mips_linux_syscall_next_pc and surroundings as advised by Pedro Alves. After this patch, all tests in gdb.base/sigstep.exp pass. Build and tested on riscv64-linux-gnu.
This commit is contained in:
@ -27,6 +27,11 @@
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#include "trad-frame.h"
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#include "trad-frame.h"
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#include "gdbarch.h"
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#include "gdbarch.h"
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/* The following value is derived from __NR_rt_sigreturn in
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<include/uapi/asm-generic/unistd.h> from the Linux source tree. */
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#define RISCV_NR_rt_sigreturn 139
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/* Define the general register mapping. The kernel puts the PC at offset 0,
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/* Define the general register mapping. The kernel puts the PC at offset 0,
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gdb puts it at offset 32. Register x0 is always 0 and can be ignored.
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gdb puts it at offset 32. Register x0 is always 0 and can be ignored.
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Registers x1 to x31 are in the same place. */
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Registers x1 to x31 are in the same place. */
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@ -154,11 +159,28 @@ riscv_linux_sigframe_init (const struct tramp_frame *self,
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trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
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trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
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}
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}
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/* When FRAME is at a syscall instruction (ECALL), return the PC of the next
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instruction to be executed. */
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static CORE_ADDR
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riscv_linux_syscall_next_pc (struct frame_info *frame)
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{
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const CORE_ADDR pc = get_frame_pc (frame);
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const ULONGEST a7 = get_frame_register_unsigned (frame, RISCV_A7_REGNUM);
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if (a7 == RISCV_NR_rt_sigreturn)
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return frame_unwind_caller_pc (frame);
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return pc + 4 /* Length of the ECALL insn. */;
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}
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/* Initialize RISC-V Linux ABI info. */
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/* Initialize RISC-V Linux ABI info. */
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static void
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static void
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riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
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riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
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{
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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linux_init_abi (info, gdbarch, 0);
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linux_init_abi (info, gdbarch, 0);
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set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);
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set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);
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@ -182,6 +204,8 @@ riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
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(gdbarch, riscv_linux_iterate_over_regset_sections);
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(gdbarch, riscv_linux_iterate_over_regset_sections);
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tramp_frame_prepend_unwinder (gdbarch, &riscv_linux_sigframe);
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tramp_frame_prepend_unwinder (gdbarch, &riscv_linux_sigframe);
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tdep->syscall_next_pc = riscv_linux_syscall_next_pc;
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}
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}
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/* Initialize RISC-V Linux target support. */
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/* Initialize RISC-V Linux target support. */
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@ -1421,6 +1421,8 @@ public:
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/* These are needed for stepping over atomic sequences. */
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/* These are needed for stepping over atomic sequences. */
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LR,
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LR,
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SC,
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SC,
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/* This instruction is used to do a syscall. */
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ECALL,
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/* Other instructions are not interesting during the prologue scan, and
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/* Other instructions are not interesting during the prologue scan, and
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are ignored. */
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are ignored. */
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@ -1711,6 +1713,8 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
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decode_r_type_insn (SC, ival);
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decode_r_type_insn (SC, ival);
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else if (is_sc_d_insn (ival))
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else if (is_sc_d_insn (ival))
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decode_r_type_insn (SC, ival);
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decode_r_type_insn (SC, ival);
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else if (is_ecall_insn (ival))
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decode_i_type_insn (ECALL, ival);
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else
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else
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/* None of the other fields are valid in this case. */
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/* None of the other fields are valid in this case. */
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m_opcode = OTHER;
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m_opcode = OTHER;
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@ -3764,6 +3768,7 @@ static CORE_ADDR
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riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
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riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
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{
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{
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struct gdbarch *gdbarch = regcache->arch ();
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struct gdbarch *gdbarch = regcache->arch ();
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const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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struct riscv_insn insn;
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struct riscv_insn insn;
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CORE_ADDR next_pc;
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CORE_ADDR next_pc;
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@ -3826,6 +3831,11 @@ riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
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if (src1 >= src2)
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if (src1 >= src2)
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next_pc = pc + insn.imm_signed ();
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next_pc = pc + insn.imm_signed ();
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}
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}
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else if (insn.opcode () == riscv_insn::ECALL)
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{
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if (tdep->syscall_next_pc != nullptr)
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next_pc = tdep->syscall_next_pc (get_current_frame ());
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}
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return next_pc;
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return next_pc;
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}
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}
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@ -34,6 +34,7 @@ enum
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RISCV_FP_REGNUM = 8, /* Frame Pointer. */
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RISCV_FP_REGNUM = 8, /* Frame Pointer. */
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RISCV_A0_REGNUM = 10, /* First argument. */
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RISCV_A0_REGNUM = 10, /* First argument. */
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RISCV_A1_REGNUM = 11, /* Second argument. */
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RISCV_A1_REGNUM = 11, /* Second argument. */
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RISCV_A7_REGNUM = 17, /* Seventh argument. */
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RISCV_PC_REGNUM = 32, /* Program Counter. */
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RISCV_PC_REGNUM = 32, /* Program Counter. */
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RISCV_NUM_INTEGER_REGS = 32,
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RISCV_NUM_INTEGER_REGS = 32,
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@ -102,6 +103,9 @@ struct gdbarch_tdep
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int duplicate_frm_regnum = -1;
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int duplicate_frm_regnum = -1;
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int duplicate_fcsr_regnum = -1;
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int duplicate_fcsr_regnum = -1;
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/* Return the expected next PC assuming FRAME is stopped at a syscall
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instruction. */
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CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
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};
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};
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