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https://github.com/espressif/binutils-gdb.git
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x86: re-work operand swapping for XOP shift/rotate insns
There's no need for custom operand handling here, except for the VEX.W controlled operand swapping.
This commit is contained in:
@ -1,3 +1,11 @@
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2020-07-08 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
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Vex_2src_2): Delete.
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(OP_VexW, VexW): New.
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(xop_table): Use EXx for rotates by immediate. Use EXx and VexW
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for shifts and rotates by register.
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2020-07-08 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
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@ -88,6 +88,7 @@ static void OP_MS (int, int);
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static void OP_XS (int, int);
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static void OP_M (int, int);
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static void OP_VEX (int, int);
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static void OP_VexW (int, int);
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static void OP_EX_Vex (int, int);
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static void OP_XMM_Vex (int, int);
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static void OP_Rounding (int, int);
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@ -119,8 +120,6 @@ static void FXSAVE_Fixup (int, int);
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static void PCMPESTR_Fixup (int, int);
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static void OP_LWPCB_E (int, int);
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static void OP_LWP_E (int, int);
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static void OP_Vex_2src_1 (int, int);
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static void OP_Vex_2src_2 (int, int);
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static void MOVBE_Fixup (int, int);
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static void MOVSXD_Fixup (int, int);
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@ -410,10 +409,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define CMP { CMP_Fixup, 0 }
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#define XMM0 { XMM_Fixup, 0 }
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#define FXSAVE { FXSAVE_Fixup, 0 }
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#define Vex_2src_1 { OP_Vex_2src_1, 0 }
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#define Vex_2src_2 { OP_Vex_2src_2, 0 }
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#define Vex { OP_VEX, vex_mode }
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#define VexW { OP_VexW, vex_mode }
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#define VexScalar { OP_VEX, vex_scalar_mode }
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#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
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#define Vex128 { OP_VEX, vex128_mode }
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@ -7629,10 +7627,10 @@ static const struct dis386 xop_table[][256] = {
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{ Bad_Opcode },
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{ Bad_Opcode },
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/* c0 */
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{ "vprotb", { XM, Vex_2src_1, Ib }, 0 },
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{ "vprotw", { XM, Vex_2src_1, Ib }, 0 },
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{ "vprotd", { XM, Vex_2src_1, Ib }, 0 },
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{ "vprotq", { XM, Vex_2src_1, Ib }, 0 },
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{ "vprotb", { XM, EXx, Ib }, 0 },
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{ "vprotw", { XM, EXx, Ib }, 0 },
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{ "vprotd", { XM, EXx, Ib }, 0 },
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{ "vprotq", { XM, EXx, Ib }, 0 },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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@ -7866,19 +7864,19 @@ static const struct dis386 xop_table[][256] = {
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{ Bad_Opcode },
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{ Bad_Opcode },
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/* 90 */
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{ "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vprotb", { XM, EXx, VexW }, 0 },
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{ "vprotw", { XM, EXx, VexW }, 0 },
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{ "vprotd", { XM, EXx, VexW }, 0 },
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{ "vprotq", { XM, EXx, VexW }, 0 },
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{ "vpshlb", { XM, EXx, VexW }, 0 },
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{ "vpshlw", { XM, EXx, VexW }, 0 },
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{ "vpshld", { XM, EXx, VexW }, 0 },
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{ "vpshlq", { XM, EXx, VexW }, 0 },
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/* 98 */
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{ "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
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{ "vpshab", { XM, EXx, VexW }, 0 },
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{ "vpshaw", { XM, EXx, VexW }, 0 },
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{ "vpshad", { XM, EXx, VexW }, 0 },
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{ "vpshaq", { XM, EXx, VexW }, 0 },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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@ -15850,64 +15848,16 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
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}
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static void
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OP_Vex_2src (int bytemode, int sizeflag)
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OP_VexW (int bytemode, int sizeflag)
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{
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if (modrm.mod == 3)
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{
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int reg = modrm.rm;
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USED_REX (REX_B);
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if (rex & REX_B)
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reg += 8;
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oappend (names_xmm[reg]);
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}
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else
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{
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if (intel_syntax
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&& (bytemode == v_mode || bytemode == v_swap_mode))
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{
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bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
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used_prefixes |= (prefixes & PREFIX_DATA);
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}
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OP_E (bytemode, sizeflag);
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}
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}
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static void
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OP_Vex_2src_1 (int bytemode, int sizeflag)
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{
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if (modrm.mod == 3)
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{
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/* Skip mod/rm byte. */
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MODRM_CHECK;
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codep++;
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}
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OP_VEX (bytemode, sizeflag);
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if (vex.w)
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{
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unsigned int reg = vex.register_specifier;
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vex.register_specifier = 0;
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if (address_mode != mode_64bit)
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reg &= 7;
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oappend (names_xmm[reg]);
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}
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else
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OP_Vex_2src (bytemode, sizeflag);
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}
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static void
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OP_Vex_2src_2 (int bytemode, int sizeflag)
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{
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if (vex.w)
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OP_Vex_2src (bytemode, sizeflag);
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else
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{
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unsigned int reg = vex.register_specifier;
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vex.register_specifier = 0;
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if (address_mode != mode_64bit)
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reg &= 7;
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oappend (names_xmm[reg]);
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/* Swap 2nd and 3rd operands. */
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strcpy (scratchbuf, op_out[2]);
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strcpy (op_out[2], op_out[1]);
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strcpy (op_out[1], scratchbuf);
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}
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}
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