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sim: mcore: move libsim.a creation to top-level

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The objects are still compiled in the subdir, but the creation of the
archive itself is in the top-level.  This is a required step before we
can move compilation itself up, and makes it easier to review.

The downside is that each object compile is a recursive make instead of
a single one.  On my 4 core system, it adds ~100msec to the build per
port, so it's not great, but it shouldn't be a big deal.  This will go
away of course once the top-level compiles objects.
This commit is contained in:
Mike Frysinger
2022-12-26 22:01:29 -05:00
parent ccb680718a
commit dfceaa0dc3
3 changed files with 105 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

139
sim/Makefile.in
View File

@ -231,33 +231,34 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_81 = $(m68hc11_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_82 = m68hc11/gencode
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_83 = $(m68hc11_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_84 = mcore/run
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_85 = microblaze/run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_86 = mips/run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_87 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_mips_TRUE@am__append_88 = mips/itable.h \
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_84 = mcore/libsim.a
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_85 = mcore/run
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_86 = microblaze/run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_87 = mips/run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_88 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_mips_TRUE@am__append_89 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC)
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_89 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_90 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-mode-single
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_90 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_91 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m16 \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m32
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_91 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_92 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_SRC) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-igen \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_92 = $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@am__append_93 = $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@am__append_94 = mips/multi-include.h mips/multi-run.c
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_95 = mn10300/run
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_96 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_97 = \
@SIM_ENABLE_ARCH_mips_TRUE@am__append_94 = $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@am__append_95 = mips/multi-include.h mips/multi-run.c
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_96 = mn10300/run
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_97 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_98 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
@ -266,29 +267,29 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_98 = $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_99 = $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_100 = moxie/run
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_101 = msp430/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_102 = or1k/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_103 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_104 = $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_100 = $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_101 = moxie/run
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_102 = msp430/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_103 = or1k/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_104 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_105 = $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_106 = ppc/run ppc/psim
@SIM_ENABLE_ARCH_pru_TRUE@am__append_107 = pru/run
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_108 = riscv/run
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_109 = rl78/run
@SIM_ENABLE_ARCH_rx_TRUE@am__append_110 = rx/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 = sh/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 = \
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_106 = $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_107 = ppc/run ppc/psim
@SIM_ENABLE_ARCH_pru_TRUE@am__append_108 = pru/run
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_109 = riscv/run
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_110 = rl78/run
@SIM_ENABLE_ARCH_rx_TRUE@am__append_111 = rx/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 = sh/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c
@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_sh_TRUE@am__append_114 = sh/gencode
@SIM_ENABLE_ARCH_sh_TRUE@am__append_115 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_116 = v850/run
@SIM_ENABLE_ARCH_v850_TRUE@am__append_117 = \
@SIM_ENABLE_ARCH_sh_TRUE@am__append_114 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_sh_TRUE@am__append_115 = sh/gencode
@SIM_ENABLE_ARCH_sh_TRUE@am__append_116 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_117 = v850/run
@SIM_ENABLE_ARCH_v850_TRUE@am__append_118 = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
@ -297,8 +298,8 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h
@SIM_ENABLE_ARCH_v850_TRUE@am__append_118 = $(v850_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_119 = $(v850_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_120 = $(v850_BUILD_OUTPUTS)
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
@ -661,6 +662,16 @@ m68hc11_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/sim-resume.o
am_m68hc11_libsim_a_OBJECTS =
m68hc11_libsim_a_OBJECTS = $(am_m68hc11_libsim_a_OBJECTS)
mcore_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_DEPENDENCIES = \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/interp.o $(patsubst \
@SIM_ENABLE_ARCH_mcore_TRUE@ %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_mcore_TRUE@ %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/modules.o mcore/sim-resume.o
am_mcore_libsim_a_OBJECTS =
mcore_libsim_a_OBJECTS = $(am_mcore_libsim_a_OBJECTS)
@SIM_ENABLE_IGEN_TRUE@am__EXEEXT_1 = $(IGEN) igen/filter$(EXEEXT) \
@SIM_ENABLE_IGEN_TRUE@ igen/gen$(EXEEXT) igen/ld-cache$(EXEEXT) \
@SIM_ENABLE_IGEN_TRUE@ igen/ld-decode$(EXEEXT) \
@ -994,11 +1005,12 @@ SOURCES = $(aarch64_libsim_a_SOURCES) $(arm_libsim_a_SOURCES) \
$(igen_libigen_a_SOURCES) $(iq2000_libsim_a_SOURCES) \
$(lm32_libsim_a_SOURCES) $(m32c_libsim_a_SOURCES) \
$(m32r_libsim_a_SOURCES) $(m68hc11_libsim_a_SOURCES) \
$(aarch64_run_SOURCES) $(arm_run_SOURCES) $(avr_run_SOURCES) \
$(bfin_run_SOURCES) $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) \
$(cr16_run_SOURCES) $(cris_run_SOURCES) \
$(cris_rvdummy_SOURCES) $(d10v_gencode_SOURCES) \
$(d10v_run_SOURCES) $(erc32_run_SOURCES) erc32/sis.c \
$(mcore_libsim_a_SOURCES) $(aarch64_run_SOURCES) \
$(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \
$(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \
$(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \
$(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \
$(erc32_run_SOURCES) erc32/sis.c \
$(example_synacor_run_SOURCES) $(frv_run_SOURCES) \
$(ft32_run_SOURCES) $(h8300_run_SOURCES) \
$(igen_filter_SOURCES) $(igen_gen_SOURCES) \
@ -1551,7 +1563,7 @@ SUBDIRS = @subdirs@ $(SIM_SUBDIRS)
AM_MAKEFLAGS = SIM_NEW_COMMON_OBJS_="$(SIM_NEW_COMMON_OBJS)" \
$(am__append_3) $(am__append_16) $(am__append_30) \
$(am__append_63) $(am__append_74) $(am__append_80) \
$(am__append_87) $(am__append_96)
$(am__append_88) $(am__append_97)
pkginclude_HEADERS = $(am__append_1)
noinst_LIBRARIES = common/libcommon.a $(am__append_5) $(am__append_8) \
$(am__append_10) $(am__append_12) $(am__append_14) \
@ -1559,17 +1571,17 @@ noinst_LIBRARIES = common/libcommon.a $(am__append_5) $(am__append_8) \
$(am__append_35) $(am__append_41) $(am__append_45) \
$(am__append_47) $(am__append_52) $(am__append_54) \
$(am__append_56) $(am__append_61) $(am__append_67) \
$(am__append_72) $(am__append_78)
$(am__append_72) $(am__append_78) $(am__append_84)
BUILT_SOURCES = $(am__append_19) $(am__append_24) $(am__append_32) \
$(am__append_37) $(am__append_49) $(am__append_58) \
$(am__append_64) $(am__append_75) $(am__append_88) \
$(am__append_97) $(am__append_103) $(am__append_112) \
$(am__append_117)
$(am__append_64) $(am__append_75) $(am__append_89) \
$(am__append_98) $(am__append_104) $(am__append_113) \
$(am__append_118)
CLEANFILES = common/version.c common/version.c-stamp \
testsuite/common/bits-gen testsuite/common/bits32m0.c \
testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
testsuite/common/bits64m63.c
DISTCLEANFILES = $(am__append_94)
DISTCLEANFILES = $(am__append_95)
MOSTLYCLEANFILES = core $(common_HW_CONFIG_H_TARGETS) $(patsubst \
%,%/stamp-hw,$(SIM_ENABLED_ARCHES)) \
$(common_GEN_MODULES_C_TARGETS) $(patsubst \
@ -1578,8 +1590,8 @@ MOSTLYCLEANFILES = core $(common_HW_CONFIG_H_TARGETS) $(patsubst \
$(am__append_27) $(am__append_34) $(am__append_40) \
$(am__append_51) $(am__append_60) $(am__append_66) \
$(am__append_71) $(am__append_77) $(am__append_83) \
$(am__append_93) $(am__append_99) $(am__append_105) \
$(am__append_115) $(am__append_119)
$(am__append_94) $(am__append_100) $(am__append_106) \
$(am__append_116) $(am__append_120)
AM_CFLAGS = $(WERROR_CFLAGS) $(WARN_CFLAGS)
AM_CPPFLAGS = $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \
$(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \
@ -1593,9 +1605,9 @@ SIM_ALL_RECURSIVE_DEPS = common/libcommon.a \
$(am__append_4) $(am__append_20) $(am__append_25) \
$(am__append_33) $(am__append_38) $(am__append_50) \
$(am__append_59) $(am__append_65) $(am__append_69) \
$(am__append_76) $(am__append_81) $(am__append_92) \
$(am__append_98) $(am__append_104) $(am__append_113) \
$(am__append_118)
$(am__append_76) $(am__append_81) $(am__append_93) \
$(am__append_99) $(am__append_105) $(am__append_114) \
$(am__append_119)
SIM_INSTALL_DATA_LOCAL_DEPS =
SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_43)
SIM_UNINSTALL_LOCAL_DEPS = $(am__append_44)
@ -2294,6 +2306,15 @@ testsuite_common_CPPFLAGS = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.c
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_gencode_SOURCES = m68hc11/gencode.c
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_SOURCES =
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(common_libcommon_a_OBJECTS) \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/interp.o \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/modules.o \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/sim-resume.o
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_SOURCES =
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_LDADD = \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/nrun.o \
@ -2358,8 +2379,8 @@ testsuite_common_CPPFLAGS = \
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_89) $(am__append_90) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_91)
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_90) $(am__append_91) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_92)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@ -2918,6 +2939,14 @@ m68hc11/libsim.a: $(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_DEPENDENCIES) $
$(AM_V_at)-rm -f m68hc11/libsim.a
$(AM_V_AR)$(m68hc11_libsim_a_AR) m68hc11/libsim.a $(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_LIBADD)
$(AM_V_at)$(RANLIB) m68hc11/libsim.a
mcore/$(am__dirstamp):
@$(MKDIR_P) mcore
@: > mcore/$(am__dirstamp)
mcore/libsim.a: $(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_DEPENDENCIES) $(EXTRA_mcore_libsim_a_DEPENDENCIES) mcore/$(am__dirstamp)
$(AM_V_at)-rm -f mcore/libsim.a
$(AM_V_AR)$(mcore_libsim_a_AR) mcore/libsim.a $(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIBADD)
$(AM_V_at)$(RANLIB) mcore/libsim.a
clean-checkPROGRAMS:
@list='$(check_PROGRAMS)'; test -n "$$list" || exit 0; \
@ -3092,9 +3121,6 @@ m68hc11/gencode.$(OBJEXT): m68hc11/$(am__dirstamp) \
m68hc11/run$(EXEEXT): $(m68hc11_run_OBJECTS) $(m68hc11_run_DEPENDENCIES) $(EXTRA_m68hc11_run_DEPENDENCIES) m68hc11/$(am__dirstamp)
@rm -f m68hc11/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(m68hc11_run_OBJECTS) $(m68hc11_run_LDADD) $(LIBS)
mcore/$(am__dirstamp):
@$(MKDIR_P) mcore
@: > mcore/$(am__dirstamp)
mcore/run$(EXEEXT): $(mcore_run_OBJECTS) $(mcore_run_DEPENDENCIES) $(EXTRA_mcore_run_DEPENDENCIES) mcore/$(am__dirstamp)
@rm -f mcore/run$(EXEEXT)
@ -4618,6 +4644,13 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc12int.c: m68hc11/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_GEN)$< -m6812 >$@
@SIM_ENABLE_ARCH_mcore_TRUE@$(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIBADD): mcore/hw-config.h
@SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: mcore/%.c
@SIM_ENABLE_ARCH_mcore_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: common/%.c
@SIM_ENABLE_ARCH_mcore_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_mips_TRUE@mips/modules.c: | $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_IGEN_ITABLE): mips/stamp-igen-itable

5
sim/mcore/Makefile.in
View File

@ -17,9 +17,6 @@
## COMMON_PRE_CONFIG_FRAG
SIM_OBJS = \
interp.o \
$(SIM_NEW_COMMON_OBJS) \
sim-resume.o
SIM_LIBSIM =
## COMMON_POST_CONFIG_FRAG

18
sim/mcore/local.mk
View File

@ -16,6 +16,24 @@
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
%C%_libsim_a_SOURCES =
%C%_libsim_a_LIBADD = \
$(common_libcommon_a_OBJECTS) \
%D%/interp.o \
$(patsubst %,%D%/%,$(SIM_NEW_COMMON_OBJS)) \
$(patsubst %,%D%/dv-%.o,$(SIM_HW_DEVICES)) \
%D%/modules.o \
%D%/sim-resume.o
$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h
noinst_LIBRARIES += %D%/libsim.a
%D%/%.o: %D%/%.c
$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
%D%/%.o: common/%.c
$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
%C%_run_SOURCES =
%C%_run_LDADD = \
%D%/nrun.o \