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ppc/svp64: support svremap instruction

Browse Source 
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/remap/#svremap
https://libre-soc.org/openpower/isa/simplev/
This commit is contained in:
Dmitry Selyutin
2022-07-25 16:10:19 +03:00
committed by Alan Modra
parent baf97ef24f
commit df0030b531
4 changed files with 45 additions and 0 deletions
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1
gas/testsuite/gas/ppc/ppc.exp
View File

@ -158,3 +158,4 @@ run_dump_test "raw"
run_dump_test "setvl"
run_dump_test "svstep"
run_dump_test "svshape"
run_dump_test "svremap"

16
gas/testsuite/gas/ppc/svremap.d Normal file
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@ -0,0 +1,16 @@
#as: -mlibresoc
#objdump: -dr -Mlibresoc
.*: file format .*
Disassembly of section \.text:
0+ <\.text>:
.*: (39 00 00 58|58 00 00 39) svremap 0,0,0,0,0,0,0
.*: (39 00 e0 5b|5b e0 00 39) svremap 31,0,0,0,0,0,0
.*: (39 00 18 58|58 18 00 39) svremap 0,3,0,0,0,0,0
.*: (39 00 06 58|58 06 00 39) svremap 0,0,3,0,0,0,0
.*: (39 80 01 58|58 01 80 39) svremap 0,0,0,3,0,0,0
.*: (39 60 00 58|58 00 60 39) svremap 0,0,0,0,3,0,0
.*: (39 18 00 58|58 00 18 39) svremap 0,0,0,0,0,3,0
.*: (39 04 18 58|58 18 04 39) svremap 0,3,0,0,0,0,1

8
gas/testsuite/gas/ppc/svremap.s Normal file
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@ -0,0 +1,8 @@
svremap 0,0,0,0,0,0,0
svremap 31,0,0,0,0,0,0
svremap 0,3,0,0,0,0,0
svremap 0,0,3,0,0,0,0
svremap 0,0,0,3,0,0,0
svremap 0,0,0,0,3,0,0
svremap 0,0,0,0,0,3,0
svremap 0,3,0,0,0,0,1

20
opcodes/ppc-opc.c
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@ -2849,6 +2849,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The RM field in an X form instruction. */
#define RM BOP + 1
#define DD RM
#define mo1 RM
{ 0x3, 11, NULL, NULL, 0 },
#define BH RM + 1
@ -3507,6 +3508,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The TO field in a D or X form instruction. */
#define TO TBR + 1
#define DUI TO
#define SVme TO
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
@ -3620,6 +3622,8 @@ const struct powerpc_operand powerpc_operands[] =
#define PSWM WS + 1
/* The BO16 field in a BD8 form instruction. */
#define BO16 PSWM
/* The pst field in a SVRM form instruction. */
#define pst PSWM
{ 0x1, 10, 0, 0, 0 },
/* IDX bits for quantization in the pair singles instructions. */
@ -3657,6 +3661,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
#define SP PRS + 1
#define mi0 SP
{ 0x3, 19, NULL, NULL, 0 },
#define S SP + 1
@ -3824,6 +3829,7 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 },
#define HH DDD + 1
#define mo0 HH
{ 0x3, 13, NULL, NULL, 0 },
#define SVi HH + 1
@ -3852,6 +3858,12 @@ const struct powerpc_operand powerpc_operands[] =
#define SVrm SVzd + 1
{ 0xf, 7, NULL, NULL, 0 },
#define mi1 SVrm + 1
{ 0x3, 17, NULL, NULL, 0 },
#define mi2 mi1 + 1
{ 0x3, 15, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@ -4740,6 +4752,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
| (((uint64_t)(xop)) & 0x3f))
#define SVM_MASK SVM (0x3f, 0x3f)
/* An SVRM form instruction. */
#define SVRM(op, xop) \
(OP (op) \
| (((uint64_t)(xop)) & 0x3f))
#define SVRM_MASK SVRM (0x3f, 0x3f)
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
@ -6817,6 +6835,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}},
{"svremap", SVRM(22,57), SVRM_MASK, SVP64, PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},