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AArch64: Fix Diagnostic messaging for LD/ST Exclusive.
A summary of what this patch set fixes: For instructions STXR w0,x2,[x0] STLXR w0,x2,[x0] The warning we emit currently is misleading: Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]' it ought to be: Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]' For instructions: ldaxp x0,x0,[x0] ldxp x0,x0,[x0] The warning we emit is incorrect Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]' Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]' it ought to be: Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]' Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]' For instructions stlxp w0, x2, x2, [x0] stxp w0, x2, x2, [x0] We don't emit any warning when it ought to be: Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]' gas/ChangeLog: 2021-04-09 Tejas Belagod <tejas.belagod@arm.com> * config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages for LD/ST Exclusive instructions. * testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP. * testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
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committed by
Tamar Christina

parent
52efda8266
commit
dd17020328
@ -1,3 +1,10 @@
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2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
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* config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages
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for LD/ST Exclusive instructions.
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* testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP.
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* testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
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2021-04-09 Alan Modra <amodra@gmail.com>
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* testsuite/gas/ppc/prefix-pcrel.d: Update expected output.
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@ -7156,18 +7156,49 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
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break;
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case ldstexcl:
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/* It is unpredictable if the destination and status registers are the
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same. */
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if ((aarch64_get_operand_class (opnds[0].type)
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== AARCH64_OPND_CLASS_INT_REG)
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&& (aarch64_get_operand_class (opnds[1].type)
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== AARCH64_OPND_CLASS_INT_REG)
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&& (opnds[0].reg.regno == opnds[1].reg.regno
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|| opnds[0].reg.regno == opnds[2].reg.regno))
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as_warn (_("unpredictable: identical transfer and status registers"
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" --`%s'"),
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str);
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== AARCH64_OPND_CLASS_INT_REG))
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{
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if ((opcode->opcode & (1 << 22)))
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{
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/* It is unpredictable if load-exclusive pair with Rt == Rt2. */
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if ((opcode->opcode & (1 << 21))
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&& opnds[0].reg.regno == opnds[1].reg.regno)
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as_warn (_("unpredictable load of register pair -- `%s'"), str);
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}
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else
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{
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/* Store-Exclusive is unpredictable if Rt == Rs. */
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if (opnds[0].reg.regno == opnds[1].reg.regno)
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as_warn
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(_("unpredictable: identical transfer and status registers"
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" --`%s'"),str);
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if (opnds[0].reg.regno == opnds[2].reg.regno)
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{
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if (!(opcode->opcode & (1 << 21)))
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/* Store-Exclusive is unpredictable if Rn == Rs. */
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as_warn
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(_("unpredictable: identical base and status registers"
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" --`%s'"),str);
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else
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/* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
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as_warn
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(_("unpredictable: "
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"identical transfer and status registers"
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" --`%s'"),str);
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}
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/* Store-Exclusive pair is unpredictable if Rn == Rs. */
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if ((opcode->opcode & (1 << 21))
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&& opnds[0].reg.regno == opnds[3].reg.regno
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&& opnds[3].reg.regno != REG_SP)
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as_warn (_("unpredictable: identical base and status registers"
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" --`%s'"),str);
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}
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}
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break;
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default:
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@ -175,11 +175,11 @@
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[^:]*:304: Warning: unpredictable: identical transfer and status registers --`stlxrb w26,w26,\[x0\]'
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[^:]*:305: Warning: unpredictable: identical transfer and status registers --`stlxrh w26,w26,\[x1\]'
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[^:]*:306: Warning: unpredictable: identical transfer and status registers --`stlxr w26,w26,\[x2\]'
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[^:]*:307: Warning: unpredictable: identical transfer and status registers --`stlxrb w26,w27,\[x26\]'
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[^:]*:308: Warning: unpredictable: identical transfer and status registers --`stlxrh w26,w27,\[x26\]'
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[^:]*:309: Warning: unpredictable: identical transfer and status registers --`stlxr w26,w27,\[x26\]'
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[^:]*:310: Warning: unpredictable: identical transfer and status registers --`stlxr w26,x27,\[x26\]'
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[^:]*:307: Warning: unpredictable: identical base and status registers --`stlxrb w26,w27,\[x26\]'
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[^:]*:308: Warning: unpredictable: identical base and status registers --`stlxrh w26,w27,\[x26\]'
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[^:]*:309: Warning: unpredictable: identical base and status registers --`stlxr w26,w27,\[x26\]'
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[^:]*:310: Warning: unpredictable: identical base and status registers --`stlxr w26,x27,\[x26\]'
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[^:]*:311: Warning: unpredictable: identical transfer and status registers --`stlxr w26,x26,\[x3\]'
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[^:]*:312: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x26,\[x5\]'
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[^:]*:313: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x1,\[x26\]'
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[^:]*:312: Warning: unpredictable load of register pair -- `ldxp x26,x26,\[x5\]'
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[^:]*:314: Error: expected element type rather than vector type at operand 1 -- `st4 {v0\.16b-v3\.16b}\[4\],\[x0\]'
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[^:]*:315: Warning: unpredictable: identical base and status registers --`stlxp w3,w26,w26,\[x3\]'
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@ -312,3 +312,4 @@
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ldxp x26, x26, [x5]
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ldxp x26, x1, [x26]
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st4 {v0.16b-v3.16b}[4], [x0]
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stlxp w3, w26, w26, [x3]
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