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* config/tc-mips.c (mips_cpu_info): Add an "ase" field. (MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT) (MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2) (MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete. (mips_after_parse_args): Use the new "ase" field to choose the default ASEs. (mips_cpu_info_table): Move ASEs from the "flags" field to the "ase" field.
This commit is contained in:
Richard Sandiford
@ -1,3 +1,14 @@
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2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (mips_cpu_info): Add an "ase" field.
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(MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT)
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(MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2)
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(MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete.
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(mips_after_parse_args): Use the new "ase" field to choose
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the default ASEs.
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(mips_cpu_info_table): Move ASEs from the "flags" field to the
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"ase" field.
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2013-06-18 Richard Earnshaw <rearnsha@arm.com>
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* config/tc-arm.c (symbol_preemptible): New function.
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@ -1411,21 +1411,13 @@ static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
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struct mips_cpu_info
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{
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const char *name; /* CPU or ISA name. */
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int flags; /* ASEs available, or ISA flag. */
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int flags; /* MIPS_CPU_* flags. */
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int ase; /* Set of ASEs implemented by the CPU. */
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int isa; /* ISA level. */
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int cpu; /* CPU number (default CPU if ISA). */
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};
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#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
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#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
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#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
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#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
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#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
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#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
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#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
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#define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
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#define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */
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#define MIPS_CPU_ASE_EVA 0x0200 /* CPU implements EVA ASE */
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static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
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static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
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@ -15577,58 +15569,58 @@ mips_after_parse_args (void)
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if (mips_opts.micromips == -1)
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mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
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if (mips_opts.ase_mips3d == -1)
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mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
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mips_opts.ase_mips3d = ((arch_info->ase & ASE_MIPS3D)
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&& file_mips_fp32 == 0) ? 1 : 0;
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if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
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as_bad (_("-mfp32 used with -mips3d"));
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if (mips_opts.ase_mdmx == -1)
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mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
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mips_opts.ase_mdmx = ((arch_info->ase & ASE_MDMX)
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&& file_mips_fp32 == 0) ? 1 : 0;
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if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
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as_bad (_("-mfp32 used with -mdmx"));
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if (mips_opts.ase_smartmips == -1)
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mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
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mips_opts.ase_smartmips = (arch_info->ase & ASE_SMARTMIPS) ? 1 : 0;
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if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
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as_warn (_("%s ISA does not support SmartMIPS"),
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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if (mips_opts.ase_dsp == -1)
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mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
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mips_opts.ase_dsp = (arch_info->ase & ASE_DSP) ? 1 : 0;
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if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
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as_warn (_("%s ISA does not support DSP ASE"),
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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if (mips_opts.ase_dspr2 == -1)
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{
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mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
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mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
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mips_opts.ase_dspr2 = (arch_info->ase & ASE_DSPR2) ? 1 : 0;
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mips_opts.ase_dsp = (arch_info->ase & ASE_DSP) ? 1 : 0;
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}
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if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
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as_warn (_("%s ISA does not support DSP R2 ASE"),
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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if (mips_opts.ase_eva == -1)
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mips_opts.ase_eva = (arch_info->flags & MIPS_CPU_ASE_EVA) ? 1 : 0;
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mips_opts.ase_eva = (arch_info->ase & ASE_EVA) ? 1 : 0;
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if (mips_opts.ase_eva && !ISA_SUPPORTS_EVA_ASE)
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as_warn (_("%s ISA does not support EVA ASE"),
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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if (mips_opts.ase_mt == -1)
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mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
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mips_opts.ase_mt = (arch_info->ase & ASE_MT) ? 1 : 0;
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if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
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as_warn (_("%s ISA does not support MT ASE"),
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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if (mips_opts.ase_mcu == -1)
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mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
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mips_opts.ase_mcu = (arch_info->ase & ASE_MCU) ? 1 : 0;
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if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
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as_warn (_("%s ISA does not support MCU ASE"),
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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if (mips_opts.ase_virt == -1)
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mips_opts.ase_virt = (arch_info->flags & MIPS_CPU_ASE_VIRT) ? 1 : 0;
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mips_opts.ase_virt = (arch_info->ase & ASE_VIRT) ? 1 : 0;
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if (mips_opts.ase_virt && !ISA_SUPPORTS_VIRT_ASE)
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as_warn (_("%s ISA does not support Virtualization ASE"),
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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@ -19518,167 +19510,148 @@ s_mips_mask (int reg_type)
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static const struct mips_cpu_info mips_cpu_info_table[] =
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{
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/* Entries for generic ISAs */
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{ "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
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{ "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
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{ "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
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{ "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
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{ "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
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{ "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
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{ "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
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{ "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
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{ "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
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{ "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
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{ "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
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{ "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
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{ "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
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{ "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
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{ "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
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{ "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
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/* MIPS I */
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{ "r3000", 0, ISA_MIPS1, CPU_R3000 },
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{ "r2000", 0, ISA_MIPS1, CPU_R3000 },
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{ "r3900", 0, ISA_MIPS1, CPU_R3900 },
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{ "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
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{ "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
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{ "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
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/* MIPS II */
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{ "r6000", 0, ISA_MIPS2, CPU_R6000 },
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{ "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
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/* MIPS III */
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{ "r4000", 0, ISA_MIPS3, CPU_R4000 },
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{ "r4010", 0, ISA_MIPS2, CPU_R4010 },
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{ "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
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{ "vr4111", 0, ISA_MIPS3, CPU_R4111 },
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{ "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
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{ "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
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{ "vr4181", 0, ISA_MIPS3, CPU_R4111 },
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{ "vr4300", 0, ISA_MIPS3, CPU_R4300 },
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{ "r4400", 0, ISA_MIPS3, CPU_R4400 },
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{ "r4600", 0, ISA_MIPS3, CPU_R4600 },
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{ "orion", 0, ISA_MIPS3, CPU_R4600 },
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{ "r4650", 0, ISA_MIPS3, CPU_R4650 },
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{ "r5900", 0, ISA_MIPS3, CPU_R5900 },
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{ "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
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{ "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
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{ "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
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{ "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
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{ "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
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{ "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
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{ "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
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{ "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
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{ "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
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{ "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
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{ "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
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{ "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
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{ "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
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/* ST Microelectronics Loongson 2E and 2F cores */
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{ "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
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{ "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
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{ "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
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{ "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
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/* MIPS IV */
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{ "r8000", 0, ISA_MIPS4, CPU_R8000 },
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{ "r10000", 0, ISA_MIPS4, CPU_R10000 },
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{ "r12000", 0, ISA_MIPS4, CPU_R12000 },
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{ "r14000", 0, ISA_MIPS4, CPU_R14000 },
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{ "r16000", 0, ISA_MIPS4, CPU_R16000 },
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{ "vr5000", 0, ISA_MIPS4, CPU_R5000 },
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{ "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
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{ "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
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{ "rm5200", 0, ISA_MIPS4, CPU_R5000 },
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{ "rm5230", 0, ISA_MIPS4, CPU_R5000 },
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{ "rm5231", 0, ISA_MIPS4, CPU_R5000 },
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{ "rm5261", 0, ISA_MIPS4, CPU_R5000 },
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{ "rm5721", 0, ISA_MIPS4, CPU_R5000 },
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{ "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
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{ "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
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{ "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
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{ "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
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{ "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
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{ "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
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{ "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
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{ "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
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{ "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
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{ "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
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{ "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
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{ "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
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{ "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
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{ "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
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{ "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
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{ "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
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{ "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
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/* MIPS 32 */
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{ "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
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{ "4km", 0, ISA_MIPS32, CPU_MIPS32 },
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{ "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
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{ "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
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{ "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
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{ "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
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{ "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
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{ "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
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/* MIPS 32 Release 2 */
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{ "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
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ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
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ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
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ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
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ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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/* Deprecated forms of the above. */
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{ "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
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/* 24KE is a 24K with DSP ASE, other ASEs are optional. */
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{ "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
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/* Deprecated forms of the above. */
|
||||
{ "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
/* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
|
||||
{ "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
/* Deprecated forms of the above. */
|
||||
{ "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
/* 34Kn is a 34kc without DSP. */
|
||||
{ "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
/* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
|
||||
{ "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
/* Deprecated forms of the above. */
|
||||
{ "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
/* 1004K cores are multiprocessor versions of the 34K. */
|
||||
{ "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
|
||||
ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
{ "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
|
||||
|
||||
/* MIPS 64 */
|
||||
{ "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
|
||||
{ "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
|
||||
|
||||
/* Broadcom SB-1 CPU core */
|
||||
{ "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
|
||||
ISA_MIPS64, CPU_SB1 },
|
||||
{ "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
|
||||
/* Broadcom SB-1A CPU core */
|
||||
{ "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
|
||||
ISA_MIPS64, CPU_SB1 },
|
||||
{ "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
|
||||
|
||||
{ "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
|
||||
{ "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
|
||||
|
||||
/* MIPS 64 Release 2 */
|
||||
|
||||
/* Cavium Networks Octeon CPU core */
|
||||
{ "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
|
||||
{ "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
|
||||
{ "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
|
||||
{ "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
|
||||
{ "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
|
||||
{ "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
|
||||
|
||||
/* RMI Xlr */
|
||||
{ "xlr", 0, ISA_MIPS64, CPU_XLR },
|
||||
{ "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
|
||||
|
||||
/* Broadcom XLP.
|
||||
XLP is mostly like XLR, with the prominent exception that it is
|
||||
MIPS64R2 rather than MIPS64. */
|
||||
{ "xlp", 0, ISA_MIPS64R2, CPU_XLR },
|
||||
{ "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
|
||||
|
||||
/* End marker */
|
||||
{ NULL, 0, 0, 0 }
|
||||
{ NULL, 0, 0, 0, 0 }
|
||||
};
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user