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x86: drop VecESize

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It again can be inferred from other information.

The vpopcntd templates all need to have Dword added to their memory
operands; the lack thereof was actually a bug preventing certain Intel
syntax code to assemble, so test cases get extended.
This commit is contained in:
Jan Beulich
2018-03-28 14:25:07 +02:00
committed by Jan Beulich
parent 8e6e0792d1
commit c39e5b2671
13 changed files with 7974 additions and 7946 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
gas/ChangeLog
View File

@ -1,3 +1,15 @@
2018-03-28 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_VecOperands): Replace uses of
.vecesize. Always initialize op.
* testsuite/gas/i386/avx512_vpopcntdq.s,
testsuite/gas/i386/avx512bitalg_vl.s: Add Intel syntax vpopcnt
broadcast cases with explicit operand size.
* testsuite/gas/i386/avx512_vpopcntdq.d,
testsuite/gas/i386/avx512_vpopcntdq-intel.d,
testsuite/gas/i386/avx512bitalg_vl.d
testsuite/gas/i386/avx512bitalg_vl-intel.d: Adjust expectations.
2018-03-28 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (struct Broadcast_Operation): Adjust comment.

26
gas/config/tc-i386.c
View File

@ -5051,17 +5051,14 @@ check_VecOperands (const insn_template *t)
i386_operand_type type, overlap;
/* Check if specified broadcast is supported in this instruction,
and it's applied to memory operand of DWORD or QWORD type,
depending on VecESize. */
and it's applied to memory operand of DWORD or QWORD type. */
op = i.broadcast->operand;
if (!t->opcode_modifier.broadcast
|| !i.types[op].bitfield.mem
|| (t->opcode_modifier.vecesize == 0
&& !i.types[op].bitfield.dword
&& !i.types[op].bitfield.unspecified)
|| (t->opcode_modifier.vecesize == 1
&& !i.types[op].bitfield.qword
&& !i.types[op].bitfield.unspecified))
|| (!i.types[op].bitfield.unspecified
&& (t->operand_types[op].bitfield.dword
? !i.types[op].bitfield.dword
: !i.types[op].bitfield.qword)))
{
bad_broadcast:
i.error = unsupported_broadcast;
@ -5069,7 +5066,7 @@ check_VecOperands (const insn_template *t)
}
operand_type_set (&type, 0);
switch ((t->opcode_modifier.vecesize ? 8 : 4) * i.broadcast->type)
switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
{
case 8:
type.bitfield.qword = 1;
@ -5116,15 +5113,16 @@ check_VecOperands (const insn_template *t)
break;
gas_assert (op < i.operands);
/* Check size of the memory operand. */
if ((t->opcode_modifier.vecesize == 0
&& i.types[op].bitfield.dword)
|| (t->opcode_modifier.vecesize == 1
&& i.types[op].bitfield.qword))
if (t->operand_types[op].bitfield.dword
? i.types[op].bitfield.dword
: i.types[op].bitfield.qword)
{
i.error = broadcast_needed;
return 1;
}
}
else
op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
/* Check if requested masking is supported. */
if (i.mask
@ -5171,7 +5169,7 @@ check_VecOperands (const insn_template *t)
&& i.disp_encoding != disp_encoding_32bit)
{
if (i.broadcast)
i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
else
i.memshift = t->opcode_modifier.disp8memshift;

2
gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d
View File

@ -43,6 +43,7 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 31[ ]*vpopcntd zmm6,ZMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 30[ ]*vpopcntd zmm6,DWORD PTR \[eax\]\{1to16\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 30[ ]*vpopcntd zmm6,DWORD PTR \[eax\]\{1to16\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 7f[ ]*vpopcntd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b2 00 20 00 00[ ]*vpopcntd zmm6,ZMMWORD PTR \[edx\+0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 80[ ]*vpopcntd zmm6,ZMMWORD PTR \[edx-0x2000\]
@ -57,6 +58,7 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 31[ ]*vpopcntq zmm6,ZMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 30[ ]*vpopcntq zmm6,QWORD PTR \[eax\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 30[ ]*vpopcntq zmm6,QWORD PTR \[eax\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 7f[ ]*vpopcntq zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b2 00 20 00 00[ ]*vpopcntq zmm6,ZMMWORD PTR \[edx\+0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 80[ ]*vpopcntq zmm6,ZMMWORD PTR \[edx-0x2000\]

2
gas/testsuite/gas/i386/avx512_vpopcntdq.d
View File

@ -43,6 +43,7 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 31[ ]*vpopcntd \(%ecx\),%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntd -0x1e240\(%esp,%esi,8\),%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 30[ ]*vpopcntd \(%eax\)\{1to16\},%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 7d 58 55 30[ ]*vpopcntd \(%eax\)\{1to16\},%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 7f[ ]*vpopcntd 0x1fc0\(%edx\),%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 b2 00 20 00 00[ ]*vpopcntd 0x2000\(%edx\),%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 55 72 80[ ]*vpopcntd -0x2000\(%edx\),%zmm6
@ -57,6 +58,7 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 31[ ]*vpopcntq \(%ecx\),%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 30[ ]*vpopcntq \(%eax\)\{1to8\},%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 fd 58 55 30[ ]*vpopcntq \(%eax\)\{1to8\},%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 7f[ ]*vpopcntq 0x1fc0\(%edx\),%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 b2 00 20 00 00[ ]*vpopcntq 0x2000\(%edx\),%zmm6
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 55 72 80[ ]*vpopcntq -0x2000\(%edx\),%zmm6

2
gas/testsuite/gas/i386/avx512_vpopcntdq.s
View File

@ -39,6 +39,7 @@ _start:
vpopcntd zmm6, ZMMWORD PTR [ecx] # AVX512_VPOPCNTDQ
vpopcntd zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512_VPOPCNTDQ
vpopcntd zmm6, [eax]{1to16} # AVX512_VPOPCNTDQ
vpopcntd zmm6, DWORD PTR [eax]{1to16} # AVX512_VPOPCNTDQ
vpopcntd zmm6, ZMMWORD PTR [edx+8128] # AVX512_VPOPCNTDQ Disp8
vpopcntd zmm6, ZMMWORD PTR [edx+8192] # AVX512_VPOPCNTDQ
vpopcntd zmm6, ZMMWORD PTR [edx-8192] # AVX512_VPOPCNTDQ Disp8
@ -53,6 +54,7 @@ _start:
vpopcntq zmm6, ZMMWORD PTR [ecx] # AVX512_VPOPCNTDQ
vpopcntq zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512_VPOPCNTDQ
vpopcntq zmm6, [eax]{1to8} # AVX512_VPOPCNTDQ
vpopcntq zmm6, QWORD PTR [eax]{1to8} # AVX512_VPOPCNTDQ
vpopcntq zmm6, ZMMWORD PTR [edx+8128] # AVX512_VPOPCNTDQ Disp8
vpopcntq zmm6, ZMMWORD PTR [edx+8192] # AVX512_VPOPCNTDQ
vpopcntq zmm6, ZMMWORD PTR [edx-8192] # AVX512_VPOPCNTDQ Disp8

4
gas/testsuite/gas/i386/avx512bitalg_vl-intel.d
View File

@ -78,19 +78,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 72 7f[ ]*vpopcntd xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
[ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 72 7f[ ]*vpopcntd xmm6\{k7\},DWORD PTR \[edx\+0x1fc\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 32[ ]*vpopcntd xmm6\{k7\},DWORD PTR \[edx\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 f5[ ]*vpopcntd ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f2 7d af 55 f5[ ]*vpopcntd ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 72 7f[ ]*vpopcntd ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\]
[ ]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 72 7f[ ]*vpopcntd ymm6\{k7\},DWORD PTR \[edx\+0x1fc\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 32[ ]*vpopcntd ymm6\{k7\},DWORD PTR \[edx\]\{1to8\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 f5[ ]*vpopcntq xmm6\{k7\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 55 f5[ ]*vpopcntq xmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq xmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 72 7f[ ]*vpopcntq xmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 1f 55 72 7f[ ]*vpopcntq xmm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to2\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 1f 55 32[ ]*vpopcntq xmm6\{k7\},QWORD PTR \[edx\]\{1to2\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 f5[ ]*vpopcntq ymm6\{k7\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 55 f5[ ]*vpopcntq ymm6\{k7\}\{z\},ymm5
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq ymm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 72 7f[ ]*vpopcntq ymm6\{k7\},YMMWORD PTR \[edx\+0xfe0\]
[ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 72 7f[ ]*vpopcntq ymm6\{k7\},QWORD PTR \[edx\+0x3f8\]\{1to4\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 32[ ]*vpopcntq ymm6\{k7\},QWORD PTR \[edx\]\{1to4\}
#pass

4
gas/testsuite/gas/i386/avx512bitalg_vl.d
View File

@ -78,19 +78,23 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 0f 55 72 7f[ ]*vpopcntd 0x7f0\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 72 7f[ ]*vpopcntd 0x1fc\(%edx\)\{1to4\},%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 1f 55 32[ ]*vpopcntd \(%edx\)\{1to4\},%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 f5[ ]*vpopcntd %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d af 55 f5[ ]*vpopcntd %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntd -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 2f 55 72 7f[ ]*vpopcntd 0xfe0\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 72 7f[ ]*vpopcntd 0x1fc\(%edx\)\{1to8\},%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 7d 3f 55 32[ ]*vpopcntd \(%edx\)\{1to8\},%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 f5[ ]*vpopcntq %xmm5,%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 8f 55 f5[ ]*vpopcntq %xmm5,%xmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 0f 55 72 7f[ ]*vpopcntq 0x7f0\(%edx\),%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 1f 55 72 7f[ ]*vpopcntq 0x3f8\(%edx\)\{1to2\},%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 1f 55 32[ ]*vpopcntq \(%edx\)\{1to2\},%xmm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 f5[ ]*vpopcntq %ymm5,%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd af 55 f5[ ]*vpopcntq %ymm5,%ymm6\{%k7\}\{z\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 b4 f4 c0 1d fe ff[ ]*vpopcntq -0x1e240\(%esp,%esi,8\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 2f 55 72 7f[ ]*vpopcntq 0xfe0\(%edx\),%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 72 7f[ ]*vpopcntq 0x3f8\(%edx\)\{1to4\},%ymm6\{%k7\}
[ ]*[a-f0-9]+:[ ]*62 f2 fd 3f 55 32[ ]*vpopcntq \(%edx\)\{1to4\},%ymm6\{%k7\}
#pass

4
gas/testsuite/gas/i386/avx512bitalg_vl.s
View File

@ -81,19 +81,23 @@ _start:
vpopcntd xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL}
vpopcntd xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{BITALG,VL} Disp8
vpopcntd xmm6{k7}, [edx+508]{1to4} # AVX512{BITALG,VL} Disp8
vpopcntd xmm6{k7}, DWORD PTR [edx]{1to4} # AVX512{BITALG,VL}
vpopcntd ymm6{k7}, ymm5 # AVX512{BITALG,VL}
vpopcntd ymm6{k7}{z}, ymm5 # AVX512{BITALG,VL}
vpopcntd ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL}
vpopcntd ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{BITALG,VL} Disp8
vpopcntd ymm6{k7}, [edx+508]{1to8} # AVX512{BITALG,VL} Disp8
vpopcntd ymm6{k7}, DWORD PTR [edx]{1to8} # AVX512{BITALG,VL}
vpopcntq xmm6{k7}, xmm5 # AVX512{BITALG,VL}
vpopcntq xmm6{k7}{z}, xmm5 # AVX512{BITALG,VL}
vpopcntq xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL}
vpopcntq xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{BITALG,VL} Disp8
vpopcntq xmm6{k7}, [edx+1016]{1to2} # AVX512{BITALG,VL} Disp8
vpopcntq xmm6{k7}, QWORD PTR [edx]{1to2} # AVX512{BITALG,VL}
vpopcntq ymm6{k7}, ymm5 # AVX512{BITALG,VL}
vpopcntq ymm6{k7}{z}, ymm5 # AVX512{BITALG,VL}
vpopcntq ymm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{BITALG,VL}
vpopcntq ymm6{k7}, YMMWORD PTR [edx+4064] # AVX512{BITALG,VL} Disp8
vpopcntq ymm6{k7}, [edx+1016]{1to4} # AVX512{BITALG,VL} Disp8
vpopcntq ymm6{k7}, QWORD PTR [edx]{1to4} # AVX512{BITALG,VL

8
opcodes/ChangeLog
View File

@ -1,3 +1,11 @@
2018-03-28 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (opcode_modifiers): Delete VecESize.
* i386-opc.h (VecESize): Delete.
(struct i386_opcode_modifier): Delete vecesize.
* i386-opc.tbl: Drop VecESize.
* i386-tlb.h: Re-generate.
2018-03-28 Jan Beulich <jbeulich@suse.com>
* i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,

1
opcodes/i386-gen.c
View File

@ -638,7 +638,6 @@ static bitfield opcode_modifiers[] =
BITFIELD (NoAVX),
BITFIELD (EVex),
BITFIELD (Masking),
BITFIELD (VecESize),
BITFIELD (Broadcast),
BITFIELD (StaticRounding),
BITFIELD (SAE),

7
opcodes/i386-opc.h
View File

@ -566,12 +566,6 @@ enum
#define BOTH_MASKING 3
Masking,
/* Input element size of vector insn:
0: 32bit.
1: 64bit.
*/
VecESize,
Broadcast,
/* Static rounding control is supported. */
@ -661,7 +655,6 @@ typedef struct i386_opcode_modifier
unsigned int noavx:1;
unsigned int evex:3;
unsigned int masking:2;
unsigned int vecesize:1;
unsigned int broadcast:1;
unsigned int staticrounding:1;
unsigned int sae:1;

1078
opcodes/i386-opc.tbl
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File diff suppressed because it is too large Load Diff

14770
opcodes/i386-tbl.h
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File diff suppressed because it is too large Load Diff