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RISC-V: Correct the requirement of compressed floating point instructions

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2018-08-31  Kito Cheng  <kito@andestech.com>
gas/
	* testsuite/gas/riscv/c-fld-fsd-fail.d: New.
	* testsuite/gas/riscv/c-fld-fsd-fail.l: Likewise.
	* testsuite/gas/riscv/c-fld-fsd-fail.s: Likewise.
opcodes/
	* riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
	compressed floating point instructions.
This commit is contained in:
Jim Wilson
2018-08-31 12:23:05 -07:00
parent c8c8163573
commit be192bc284
6 changed files with 36 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
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@ -1,3 +1,9 @@
2018-08-31 Kito Cheng <kito@andestech.com>
* testsuite/gas/riscv/c-fld-fsd-fail.d: New.
* testsuite/gas/riscv/c-fld-fsd-fail.l: Likewise.
* testsuite/gas/riscv/c-fld-fsd-fail.s: Likewise.
2018-08-31 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/elf/section14.d: Change skip to xfail.

3
gas/testsuite/gas/riscv/c-fld-fsd-fail.d Normal file
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@ -0,0 +1,3 @@
#as: -march=rv32ic
#source: c-fld-fsd-fail.s
#error-output: c-fld-fsd-fail.l

3
gas/testsuite/gas/riscv/c-fld-fsd-fail.l Normal file
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@ -0,0 +1,3 @@
.*: Assembler messages:
.*: Error: unrecognized opcode `fld fa0,0\(a0\)'
.*: Error: unrecognized opcode `fsd fa0,0\(a0\)'

3
gas/testsuite/gas/riscv/c-fld-fsd-fail.s Normal file
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@ -0,0 +1,3 @@
target:
fld fa0, 0(a0)
fsd fa0, 0(a0)

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2018-08-31 Kito Cheng <kito@andestech.com>
* riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
compressed floating point instructions.
2018-08-30 Kito Cheng <kito@andestech.com>
* riscv-dis.c (riscv_disassemble_insn): Check XLEN by

32
opcodes/riscv-opc.c
View File

@ -509,12 +509,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 },
{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 },
{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 },
{"flw", 32, {"C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 32, {"C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 32, {"F", "C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 0, {"F", 0}, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"flw", 0, {"F", 0}, "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO },
{"fsw", 32, {"C", 0}, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"fsw", 32, {"C", 0}, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"fsw", 32, {"F", "C", 0}, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"fsw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"fsw", 0, {"F", 0}, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"fsw", 0, {"F", 0}, "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO },
@ -574,12 +574,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"fcvt.s.lu", 64, {"F", 0}, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
/* Double-precision floating-point instruction subset */
{"fld", 0, {"C", 0}, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fld", 0, {"C", 0}, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fld", 0, {"D", "C", 0}, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fld", 0, {"D", "C", 0}, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fld", 0, {"D", 0}, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"fld", 0, {"D", 0}, "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO },
{"fsd", 0, {"C", 0}, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fsd", 0, {"C", 0}, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fsd", 0, {"D", "C", 0}, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fsd", 0, {"D", "C", 0}, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fsd", 0, {"D", 0}, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"fsd", 0, {"D", 0}, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO },
{"fmv.d", 0, {"D", 0}, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
@ -733,14 +733,14 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.ld", 64, {"C", 0}, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.sdsp", 64, {"C", 0}, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.sd", 64, {"C", 0}, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.fldsp", 0, {"C", 0}, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.fld", 0, {"C", 0}, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.fsdsp", 0, {"C", 0}, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.fsd", 0, {"C", 0}, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.flwsp", 32, {"C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
{"c.flw", 32, {"C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"c.fswsp", 32, {"C", 0}, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
{"c.fsw", 32, {"C", 0}, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"c.fldsp", 0, {"D", "C", 0}, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.fld", 0, {"D", "C", 0}, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.fsdsp", 0, {"D", "C", 0}, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.fsd", 0, {"D", "C", 0}, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"c.flwsp", 32, {"F", "C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
{"c.flw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"c.fswsp", 32, {"F", "C", 0}, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
{"c.fsw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
/* Supervisor instructions */
{"csrr", 0, {"I", 0}, "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS },