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AArch64: Add negative tests for Armv8.3-a complex number instructions instructions.

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This patch just adds a few negative tests for the Armv8.3-a complex instructions.
These already do the right disassembly without needing a verifier, but adding
some tests to make sure that stays that way.

gas/ChangeLog:

	* testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test.
	* testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.
This commit is contained in:
Tamar Christina
2019-02-07 16:58:29 +00:00
parent 6456d318aa
commit bd756351a6
3 changed files with 131 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
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@ -1,3 +1,8 @@
2019-02-07 Tamar Christina <tamar.christina@arm.com>
* testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test.
* testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.
2019-02-07 Tamar Christina <tamar.christina@arm.com>
PR binutils/23212

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gas/testsuite/gas/aarch64/undefined_advsimd_armv8_3.d Normal file
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#as: -march=armv8.3-a
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
[^:]+:\s+6ec3c441 fcmla v1.2d, v2.2d, v3.2d, #0
[^:]+:\s+6e03c441 .inst 0x6e03c441 ; undefined
[^:]+:\s+2ec3c441 .inst 0x2ec3c441 ; undefined
[^:]+:\s+2e83c441 fcmla v1.2s, v2.2s, v3.2s, #0
[^:]+:\s+2e03c441 .inst 0x2e03c441 ; undefined
[^:]+:\s+2ec3c441 .inst 0x2ec3c441 ; undefined
[^:]+:\s+6e83c441 fcmla v1.4s, v2.4s, v3.4s, #0
[^:]+:\s+6e03c441 .inst 0x6e03c441 ; undefined
[^:]+:\s+2ec3c441 .inst 0x2ec3c441 ; undefined
[^:]+:\s+2e43c441 fcmla v1.4h, v2.4h, v3.4h, #0
[^:]+:\s+2e03c441 .inst 0x2e03c441 ; undefined
[^:]+:\s+2ec3c441 .inst 0x2ec3c441 ; undefined
[^:]+:\s+6e43c441 fcmla v1.8h, v2.8h, v3.8h, #0
[^:]+:\s+6e03c441 .inst 0x6e03c441 ; undefined
[^:]+:\s+2ec3c441 .inst 0x2ec3c441 ; undefined
[^:]+:\s+6f831041 fcmla v1.4s, v2.4s, v3.s\[0\], #0
[^:]+:\s+6f031041 .inst 0x6f031041 ; undefined
[^:]+:\s+6fc31041 .inst 0x6fc31041 ; undefined
[^:]+:\s+2f431841 .inst 0x2f431841 ; undefined
[^:]+:\s+6fa31041 .inst 0x6fa31041 ; undefined
[^:]+:\s+2f831041 .inst 0x2f831041 ; undefined
[^:]+:\s+2f431041 fcmla v1.4h, v2.4h, v3.h\[0\], #0
[^:]+:\s+2f031041 .inst 0x2f031041 ; undefined
[^:]+:\s+2fc31041 .inst 0x2fc31041 ; undefined
[^:]+:\s+2f431841 .inst 0x2f431841 ; undefined
[^:]+:\s+2fa31041 .inst 0x2fa31041 ; undefined
[^:]+:\s+2f831041 .inst 0x2f831041 ; undefined
[^:]+:\s+6f431041 fcmla v1.8h, v2.8h, v3.h\[0\], #0
[^:]+:\s+6f031041 .inst 0x6f031041 ; undefined
[^:]+:\s+6fc31041 .inst 0x6fc31041 ; undefined
[^:]+:\s+2f431841 .inst 0x2f431841 ; undefined
[^:]+:\s+6fa31041 .inst 0x6fa31041 ; undefined
[^:]+:\s+2f831041 .inst 0x2f831041 ; undefined
[^:]+:\s+6ec3e441 fcadd v1.2d, v2.2d, v3.2d, #90
[^:]+:\s+6e03e441 .inst 0x6e03e441 ; undefined
[^:]+:\s+2ec3e441 .inst 0x2ec3e441 ; undefined
[^:]+:\s+2e83e441 fcadd v1.2s, v2.2s, v3.2s, #90
[^:]+:\s+2e03e441 .inst 0x2e03e441 ; undefined
[^:]+:\s+2ec3e441 .inst 0x2ec3e441 ; undefined
[^:]+:\s+6e83e441 fcadd v1.4s, v2.4s, v3.4s, #90
[^:]+:\s+6e03e441 .inst 0x6e03e441 ; undefined
[^:]+:\s+2ec3e441 .inst 0x2ec3e441 ; undefined
[^:]+:\s+2e43e441 fcadd v1.4h, v2.4h, v3.4h, #90
[^:]+:\s+2e03e441 .inst 0x2e03e441 ; undefined
[^:]+:\s+2ec3e441 .inst 0x2ec3e441 ; undefined
[^:]+:\s+6e43e441 fcadd v1.8h, v2.8h, v3.8h, #90
[^:]+:\s+6e03e441 .inst 0x6e03e441 ; undefined
[^:]+:\s+2ec3e441 .inst 0x2ec3e441 ; undefined

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gas/testsuite/gas/aarch64/undefined_advsimd_armv8_3.s Normal file
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# Generates tests to see if the following conditions make the instruction
# undefined:
#
# 1) size == 0
# 2) size == 3 && Q == 0
#
# These patterns can't be created by the assembler so instead manually encode
# them from a starting pattern.
.macro gen_insns_same opc
.inst \opc
.inst (\opc & 0xff3fffff) // size == 0
.inst ((\opc | 0xc00000) & 0xbfffffff) // size == 3 && Q == 0
.endm
# Generates tests to see if the following conditions make the instruction
# undefined:
#
# 1) size == 0 || size == 3
# 2) size == 1 && H == 1 && Q == 0
# 3) size == 2 && (L == 1 || Q == 0)
#
# These patterns can't be created by the assembler so instead manually encode
# them from a starting pattern.
.macro gen_insns_elem opc
.inst \opc
.inst (\opc & 0xff3fffff) // size == 0
.inst (\opc | 0xc00000) // size == 3
.inst ((\opc | 0x400800) & 0xbf7fffff) // size == 1 && H == 1 && Q == 0
.inst ((\opc | 0xa00000) & 0xffbfffff) // size == 2 && L == 1
.inst ((\opc | 0x800000) & 0xbfbfffff) // size == 2 && Q == 0
.endm
# fcmla v1.2d, v2.2d, v3.2d, #0
gen_insns_same 0x6ec3c441
# fcmla v1.2s, v2.2s, v3.2s, #0
gen_insns_same 0x2e83c441
# fcmla v1.4s, v2.4s, v3.4s, #0
gen_insns_same 0x6e83c441
# fcmla v1.4h, v2.4h, v3.4h, #0
gen_insns_same 0x2e43c441
# fcmla v1.8h, v2.8h, v3.8h, #0
gen_insns_same 0x6e43c441
# fcmla v1.4s, v2.4s, v3.s[0], #0
gen_insns_elem 0x6f831041
# fcmla v1.4h, v2.4h, v3.h[0], #0
gen_insns_elem 0x2f431041
# fcmla v1.8h, v2.8h, v3.h[0], #0
gen_insns_elem 0x6f431041
# fcadd v1.2d, v2.2d, v3.2d, #90
gen_insns_same 0x6ec3e441
# fcadd v1.2s, v2.2s, v3.2s, #90
gen_insns_same 0x2e83e441
# fcadd v1.4s, v2.4s, v3.4s, #90
gen_insns_same 0x6e83e441
# fcadd v1.4h, v2.4h, v3.4h, #90
gen_insns_same 0x2e43e441
# fcadd v1.8h, v2.8h, v3.8h, #90
gen_insns_same 0x6e43e441