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Add support for fcvtl and fcvtl2.

Browse Source 
sim/aarch64/
	* simulator.c (do_vec_FCVTL): New.
	(do_vec_op1): Call do_vec_FCVTL.

	sim/testsuite/sim/aarch64/
	* fcvtl.s: New.
This commit is contained in:
Jim Wilson
2017-04-08 12:06:31 -07:00
parent ae27d3fe76
commit b630840c9c
4 changed files with 112 additions and 0 deletions
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3
sim/aarch64/ChangeLog
View File

@ -1,5 +1,8 @@
2017-04-08 Jim Wilson <jim.wilson@linaro.org>
* simulator.c (do_vec_FCVTL): New.
(do_vec_op1): Call do_vec_FCVTL.
* simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
(do_scalar_vec): Add calls to new functions.

48
sim/aarch64/simulator.c
View File

@ -5468,6 +5468,47 @@ do_vec_ADDP (sim_cpu *cpu)
}
}
/* Float point vector convert to longer (precision). */
static void
do_vec_FCVTL (sim_cpu *cpu)
{
/* instr[31] = 0
instr[30] = half (0) / all (1)
instr[29,23] = 00 1110 0
instr[22] = single (0) / double (1)
instr[21,10] = 10 0001 0111 10
instr[9,5] = Rn
instr[4,0] = Rd. */
unsigned rn = INSTR (9, 5);
unsigned rd = INSTR (4, 0);
unsigned full = INSTR (30, 30);
unsigned i;
NYI_assert (31, 31, 0);
NYI_assert (29, 23, 0x1C);
NYI_assert (21, 10, 0x85E);
TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
if (INSTR (22, 22))
{
for (i = 0; i < 2; i++)
aarch64_set_vec_double (cpu, rd, i,
aarch64_get_vec_float (cpu, rn, i + 2*full));
}
else
{
HALT_NYI;
#if 0
/* TODO: Implement missing half-float support. */
for (i = 0; i < 4; i++)
aarch64_set_vec_float (cpu, rd, i,
aarch64_get_vec_halffloat (cpu, rn, i + 4*full));
#endif
}
}
static void
do_vec_FABS (sim_cpu *cpu)
{
@ -5717,6 +5758,13 @@ do_vec_op1 (sim_cpu *cpu)
case 0x33: do_vec_FMLA (cpu); return;
case 0x35: do_vec_fadd (cpu); return;
case 0x1E:
switch (INSTR (20, 16))
{
case 0x01: do_vec_FCVTL (cpu); return;
default: HALT_NYI;
}
case 0x2E:
switch (INSTR (20, 16))
{

2
sim/testsuite/sim/aarch64/ChangeLog
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@ -1,5 +1,7 @@
2017-04-08 Jim Wilson <jim.wilson@linaro.org>
* fcvtl.s: New.
* fcmXX.s: New.
2017-03-25 Jim Wilson <jim.wilson@linaro.org>

59
sim/testsuite/sim/aarch64/fcvtl.s Normal file
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@ -0,0 +1,59 @@
# mach: aarch64
# Check the FP convert to longer precision: fcvtl, fcvtl2.
# Test values 1.5, -1.5, INTMAX, and INT_MIN.
.include "testutils.inc"
.data
.align 4
input:
.word 1069547520
.word 3217031168
.word 1325400064
.word 3472883712
d1p5:
.word 0
.word 1073217536
dm1p5:
.word 0
.word -1074266112
dimax:
.word 0
.word 1105199104
dimin:
.word 0
.word -1042284544
start
adrp x0, input
add x0, x0, #:lo12:input
ld1 {v0.4s}, [x0]
fcvtl v1.2d, v0.2s
mov x1, v1.d[0]
adrp x2, d1p5
ldr x3, [x2, #:lo12:d1p5]
cmp x1, x3
bne .Lfailure
mov x1, v1.d[1]
adrp x2, dm1p5
ldr x3, [x2, #:lo12:dm1p5]
cmp x1, x3
bne .Lfailure
fcvtl2 v2.2d, v0.4s
mov x1, v2.d[0]
adrp x2, dimax
ldr x3, [x2, #:lo12:dimax]
cmp x1, x3
bne .Lfailure
mov x1, v2.d[1]
adrp x2, dimin
ldr x3, [x2, #:lo12:dimin]
cmp x1, x3
bne .Lfailure
pass
.Lfailure:
fail