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Fix SATB bit pattern. Add extra control registers.
This commit is contained in:
Nick Clifton
@ -1,3 +1,9 @@
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start-sanitize-m32rx
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Wed Apr 1 14:57:54 1998 Nick Clifton <nickc@cygnus.com>
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* m32r-opc.c: Fix SATB bit pattern. Add extra control registers.
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end-sanitize-m32rx
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Tue Mar 31 11:09:08 1998 Ian Lance Taylor <ian@cygnus.com>
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From H.J. Lu <hjl@gnu.org>:
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@ -253,13 +253,22 @@ CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
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{ "cr3", 3 },
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{ "cr4", 4 },
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{ "cr5", 5 },
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{ "cr6", 6 }
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{ "cr6", 6 },
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{ "cr7", 7 },
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{ "cr8", 8 },
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{ "cr9", 9 },
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{ "cr10", 10 },
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{ "cr11", 11 },
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{ "cr12", 12 },
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{ "cr13", 13 },
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{ "cr14", 14 },
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{ "cr15", 15 }
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};
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CGEN_KEYWORD m32r_cgen_opval_h_cr =
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{
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& m32r_cgen_opval_h_cr_entries[0],
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12
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21
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};
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/* start-sanitize-m32rx */
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@ -516,6 +525,7 @@ static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = {
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{ 0 }
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};
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
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{ INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
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{ INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
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@ -525,6 +535,8 @@ static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
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{ INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
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{ INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
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@ -534,6 +546,7 @@ static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = {
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{ INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
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{ OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
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@ -567,12 +580,14 @@ static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops[] = {
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{ 0 }
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};
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops[] = {
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
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{ OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
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{ 0 }
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};
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/* end-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
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@ -580,6 +595,7 @@ static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
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{ 0 }
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};
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
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{ INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
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@ -587,6 +603,7 @@ static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = {
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{ INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
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@ -688,6 +705,7 @@ static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = {
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{ 0 }
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};
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = {
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{ INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
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@ -696,6 +714,7 @@ static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = {
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
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@ -703,6 +722,7 @@ static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = {
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{ 0 }
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};
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = {
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
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@ -710,6 +730,7 @@ static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops[] = {
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
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{ OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
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@ -722,12 +743,14 @@ static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops[] = {
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{ 0 }
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};
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = {
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{ INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
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{ OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
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{ 0 }
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};
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/* end-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = {
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{ INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
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{ OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
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@ -741,6 +764,7 @@ static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = {
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{ 0 }
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};
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
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{ INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
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@ -748,6 +772,7 @@ static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = {
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
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{ OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
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@ -760,6 +785,7 @@ static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = {
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{ 0 }
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};
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
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{ INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
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{ INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
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@ -767,6 +793,7 @@ static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = {
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{ INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
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{ INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
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@ -871,12 +898,15 @@ static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = {
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{ 0 }
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};
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = {
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
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{ OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
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{ 0 }
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};
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = {
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{ INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
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@ -884,6 +914,8 @@ static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = {
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{ INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
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{ INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
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@ -891,6 +923,8 @@ static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = {
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{ INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
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@ -899,6 +933,8 @@ static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = {
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
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@ -906,11 +942,14 @@ static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = {
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{ 0 }
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};
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = {
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{ INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
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{ 0 }
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};
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/* end-sanitize-m32rx */
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#undef INPUT
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#undef OUTPUT
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@ -2381,7 +2420,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
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{ 1, 1, 1, 1 },
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"satb", "satb",
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{ MNEM, ' ', OP (DR), ',', OP (SR), 0 },
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{ 32, 32, 0xf0f0ffff }, 0x80000100,
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{ 32, 32, 0xf0f0ffff }, 0x80600100,
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& fmt_74_satb_ops[0],
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{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
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},
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@ -2392,7 +2431,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
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{ 1, 1, 1, 1 },
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"sath", "sath",
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{ MNEM, ' ', OP (DR), ',', OP (SR), 0 },
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{ 32, 32, 0xf0f0ffff }, 0x80000200,
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{ 32, 32, 0xf0f0ffff }, 0x80600200,
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& fmt_74_satb_ops[0],
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{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
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},
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