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x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel mode

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The operands don't allow disambiguating the insn in 64-bit mode, and
hence suffixes need to be emitted not just in AT&T mode. Achieve this
by re-using %LQ while dropping PCMPESTR_Fixup().
This commit is contained in:
Jan Beulich
2020-07-14 10:28:12 +02:00
parent c4de76066e
commit b24d668c07
7 changed files with 44 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2020-07-14 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-avx-intel.d,
testsuite/gas/i386/x86-64-sse4_2-intel.d: Adjust expectations.
2020-07-14 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/movbe-suffix.d,

4
gas/testsuite/gas/i386/x86-64-avx-intel.d
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@ -781,11 +781,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e3 79 61 f4 07 vpcmpestri xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e3 f9 61 f4 07 vpcmpestri xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c4 e3 f9 61 f4 07 vpcmpestriq xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e3 79 60 f4 07 vpcmpestrm xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e3 f9 60 f4 07 vpcmpestrm xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c4 e3 f9 60 f4 07 vpcmpestrmq xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e3 79 63 f4 07 vpcmpistri xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri xmm6,XMMWORD PTR \[rcx\],0x7

4
gas/testsuite/gas/i386/x86-64-sse4_2-intel.d
View File

@ -25,11 +25,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 38 37 c1 pcmpgtq xmm0,xmm1
[ ]*[a-f0-9]+: 66 0f 3a 61 01 00 pcmpestri xmm0,XMMWORD PTR \[rcx\],0x0
[ ]*[a-f0-9]+: 66 0f 3a 61 c1 00 pcmpestri xmm0,xmm1,0x0
[ ]*[a-f0-9]+: 66 48 0f 3a 61 01 00 rex\.W pcmpestri xmm0,XMMWORD PTR \[rcx\],0x0
[ ]*[a-f0-9]+: 66 48 0f 3a 61 01 00 pcmpestriq xmm0,XMMWORD PTR \[rcx\],0x0
[ ]*[a-f0-9]+: 66 0f 3a 61 c1 00 pcmpestri xmm0,xmm1,0x0
[ ]*[a-f0-9]+: 66 0f 3a 60 01 01 pcmpestrm xmm0,XMMWORD PTR \[rcx\],0x1
[ ]*[a-f0-9]+: 66 0f 3a 60 c1 01 pcmpestrm xmm0,xmm1,0x1
[ ]*[a-f0-9]+: 66 48 0f 3a 60 01 01 rex\.W pcmpestrm xmm0,XMMWORD PTR \[rcx\],0x1
[ ]*[a-f0-9]+: 66 48 0f 3a 60 01 01 pcmpestrmq xmm0,XMMWORD PTR \[rcx\],0x1
[ ]*[a-f0-9]+: 66 0f 3a 60 c1 01 pcmpestrm xmm0,xmm1,0x1
[ ]*[a-f0-9]+: 66 0f 3a 63 01 02 pcmpistri xmm0,XMMWORD PTR \[rcx\],0x2
[ ]*[a-f0-9]+: 66 0f 3a 63 c1 02 pcmpistri xmm0,xmm1,0x2

14
opcodes/ChangeLog
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@ -1,3 +1,17 @@
2020-07-14 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (PCMPESTR_Fixup): Delete.
(dis386): Adjust "LQ" description.
(prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
vpcmpestrm, and vpcmpestri.
(putop): Honor "cond" when handling LQ.
* i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
vcvtsi2ss and vcvtusi2ss.
* i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
vcvtsi2sd and vcvtusi2sd.
2020-07-14 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (VCMP_Fixup, VCMP): Delete.

4
opcodes/i386-dis-evex-prefix.h
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@ -28,7 +28,7 @@
/* PREFIX_EVEX_0F2A */
{
{ Bad_Opcode },
{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F2A_P_3) },
},
@ -272,7 +272,7 @@
/* PREFIX_EVEX_0F7B */
{
{ Bad_Opcode },
{ "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ "vcvtusi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ VEX_W_TABLE (EVEX_W_0F7B_P_2) },
{ VEX_W_TABLE (EVEX_W_0F7B_P_3) },
},

8
opcodes/i386-dis-evex-w.h
View File

@ -39,8 +39,8 @@
},
/* EVEX_W_0F2A_P_3 */
{
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 },
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
{ "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Ed }, 0 },
{ "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
},
/* EVEX_W_0F51_P_1 */
{
@ -245,8 +245,8 @@
},
/* EVEX_W_0F7B_P_3 */
{
{ "vcvtusi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 },
{ "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
{ "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, Ed }, 0 },
{ "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
},
/* EVEX_W_0F7E_P_1 */
{

52
opcodes/i386-dis.c
View File

@ -115,7 +115,6 @@ static void HLE_Fixup3 (int, int);
static void CMPXCHG8B_Fixup (int, int);
static void XMM_Fixup (int, int);
static void FXSAVE_Fixup (int, int);
static void PCMPESTR_Fixup (int, int);
static void MOVSXD_Fixup (int, int);
@ -2287,8 +2286,8 @@ struct dis386 {
"XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
register operands and no broadcast.
"XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
operand or no operand at all in 64bit mode, or if suffix_always
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
being false, or no operand at all in 64bit mode, or if suffix_always
is true.
"LB" => print "abs" in 64bit mode and behave as 'B' otherwise
"LS" => print "abs" in 64bit mode and behave as 'S' otherwise
@ -3703,9 +3702,9 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_0F2A */
{
{ "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
{ "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
{ "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
{ "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
{ "cvtsi2sd%LQ", { XM, Edq }, 0 },
{ "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
},
/* PREFIX_0F2B */
@ -3966,13 +3965,13 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_0FAE_REG_4_MOD_0 */
{
{ "xsave", { FXSAVE }, 0 },
{ "ptwrite%LQ", { Edq }, 0 },
{ "ptwrite{%LQ|}", { Edq }, 0 },
},
/* PREFIX_0FAE_REG_4_MOD_3 */
{
{ Bad_Opcode },
{ "ptwrite%LQ", { Edq }, 0 },
{ "ptwrite{%LQ|}", { Edq }, 0 },
},
/* PREFIX_0FAE_REG_5_MOD_0 */
@ -4592,14 +4591,14 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
{ "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
{ "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A61 */
{
{ Bad_Opcode },
{ Bad_Opcode },
{ "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
{ "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A62 */
@ -4676,9 +4675,9 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_VEX_0F2A */
{
{ Bad_Opcode },
{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 },
{ "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
{ Bad_Opcode },
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 },
{ "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
},
/* PREFIX_VEX_0F2C */
@ -9847,12 +9846,12 @@ static const struct dis386 vex_len_table[][2] = {
/* VEX_LEN_0F3A60_P_2 */
{
{ "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
{ "vpcmpestrm!%LQ", { XM, EXx, Ib }, 0 },
},
/* VEX_LEN_0F3A61_P_2 */
{
{ "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
{ "vpcmpestri!%LQ", { XM, EXx, Ib }, 0 },
},
/* VEX_LEN_0F3A62_P_2 */
@ -13644,15 +13643,15 @@ putop (const char *in_template, int sizeflag)
}
else if (l == 1 && last[0] == 'L')
{
if ((intel_syntax && need_modrm)
|| (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
: address_mode != mode_64bit)
break;
if ((rex & REX_W))
{
USED_REX (REX_W);
*obufp++ = 'q';
}
else if((address_mode == mode_64bit && need_modrm)
else if((address_mode == mode_64bit && need_modrm && cond)
|| (sizeflag & SUFFIX_ALWAYS))
*obufp++ = intel_syntax? 'd' : 'l';
}
@ -16422,27 +16421,6 @@ FXSAVE_Fixup (int bytemode, int sizeflag)
OP_M (bytemode, sizeflag);
}
static void
PCMPESTR_Fixup (int bytemode, int sizeflag)
{
/* Add proper suffix to "{,v}pcmpestr{i,m}". */
if (!intel_syntax)
{
char *p = mnemonicendp;
USED_REX (REX_W);
if (rex & REX_W)
*p++ = 'q';
else if (sizeflag & SUFFIX_ALWAYS)
*p++ = 'l';
*p = '\0';
mnemonicendp = p;
}
OP_EX (bytemode, sizeflag);
}
/* Display the destination register operand for instructions with
VEX. */