mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-19 09:14:14 +08:00
Fix arm process record for some instructions
I look at some fails in gdb.reverse/solib-precsave.exp in -mthumb, they are caused by some bugs on decoding these three instructions, uxtb, ldr and mrc. This patch adds unit tests against these three instructions, and fix these bugs by re-organizing the code to match the table in ARM ARM. gdb: 2017-03-16 Yao Qi <yao.qi@linaro.org> * arm-tdep.c [GDB_SELF_TEST]: include "selftests.h". (arm_record_test): Declare. (_initialize_arm_tdep) [GDB_SELF_TEST]: call register_self_test. (thumb_record_ld_st_reg_offset): Rewrite the opcode matching to align with the manual. (thumb_record_misc): Adjust the code order to align with the manual. (thumb2_record_decode_insn_handler): Fix instruction matching. (instruction_reader_thumb): New class. (arm_record_test): New function.
This commit is contained in:
Yao Qi
@ -1,3 +1,16 @@
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2017-03-16 Yao Qi <yao.qi@linaro.org>
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* arm-tdep.c [GDB_SELF_TEST]: include "selftests.h".
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(arm_record_test): Declare.
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(_initialize_arm_tdep) [GDB_SELF_TEST]: call register_self_test.
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(thumb_record_ld_st_reg_offset): Rewrite the opcode matching to
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align with the manual.
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(thumb_record_misc): Adjust the code order to align with the
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manual.
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(thumb2_record_decode_insn_handler): Fix instruction matching.
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(instruction_reader_thumb): New class.
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(arm_record_test): New function.
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2017-03-16 Yao Qi <yao.qi@linaro.org>
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* arm-tdep.c (abstract_memory_reader): New class.
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305
gdb/arm-tdep.c
305
gdb/arm-tdep.c
@ -69,6 +69,10 @@
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#include "features/arm/arm-with-vfpv3.c"
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#include "features/arm/arm-with-neon.c"
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#if GDB_SELF_TEST
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#include "selftest.h"
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#endif
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static int arm_debug;
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/* Macros for setting and testing a bit in a minimal symbol that marks
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@ -9584,6 +9588,11 @@ arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
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(unsigned long) tdep->lowest_pc);
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}
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namespace selftests
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{
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static void arm_record_test (void);
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}
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extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
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void
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@ -9720,6 +9729,11 @@ vfp - VFP co-processor."),
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NULL,
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NULL, /* FIXME: i18n: "ARM debugging is %s. */
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&setdebuglist, &showdebuglist);
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#if GDB_SELF_TEST
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register_self_test (selftests::arm_record_test);
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#endif
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}
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/* ARM-reversible process record data structures. */
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@ -11749,26 +11763,27 @@ thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
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if (bit (thumb_insn_r->arm_insn, 12))
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{
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/* Handle load/store register offset. */
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opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
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if (opcode2 >= 12 && opcode2 <= 15)
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uint32_t opB = bits (thumb_insn_r->arm_insn, 9, 11);
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if (opB >= 4 && opB <= 7)
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{
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/* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
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reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
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record_buf[0] = reg_src1;
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thumb_insn_r->reg_rec_count = 1;
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}
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else if (opcode2 >= 8 && opcode2 <= 10)
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else if (opB >= 0 && opB <= 2)
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{
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/* STR(2), STRB(2), STRH(2) . */
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reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
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reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
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regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
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regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
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if (8 == opcode2)
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if (0 == opB)
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record_buf_mem[0] = 4; /* STR (2). */
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else if (10 == opcode2)
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else if (2 == opB)
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record_buf_mem[0] = 1; /* STRB (2). */
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else if (9 == opcode2)
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else if (1 == opB)
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record_buf_mem[0] = 2; /* STRH (2). */
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record_buf_mem[1] = u_regval[0] + u_regval[1];
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thumb_insn_r->mem_rec_count = 1;
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@ -11784,6 +11799,7 @@ thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
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}
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else if (opcode1)
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{
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/* Special data instructions and branch and exchange */
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opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
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opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
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if ((3 == opcode2) && (!opcode3))
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@ -11924,7 +11940,7 @@ thumb_record_misc (insn_decode_record *thumb_insn_r)
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{
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struct regcache *reg_cache = thumb_insn_r->regcache;
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uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
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uint32_t opcode = 0;
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uint32_t register_bits = 0, register_count = 0;
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uint32_t index = 0, start_address = 0;
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uint32_t record_buf[24], record_buf_mem[48];
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@ -11933,81 +11949,111 @@ thumb_record_misc (insn_decode_record *thumb_insn_r)
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ULONGEST u_regval = 0;
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opcode = bits (thumb_insn_r->arm_insn, 11, 12);
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opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
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opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
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if (14 == opcode2)
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if (opcode == 0 || opcode == 1)
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{
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/* POP. */
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register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
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while (register_bits)
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{
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if (register_bits & 0x00000001)
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record_buf[index++] = register_count;
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register_bits = register_bits >> 1;
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register_count++;
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}
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record_buf[index++] = ARM_PS_REGNUM;
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record_buf[index++] = ARM_SP_REGNUM;
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thumb_insn_r->reg_rec_count = index;
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}
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else if (10 == opcode2)
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{
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/* PUSH. */
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register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
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regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
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while (register_bits)
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{
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if (register_bits & 0x00000001)
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register_count++;
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register_bits = register_bits >> 1;
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}
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start_address = u_regval - \
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(4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
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thumb_insn_r->mem_rec_count = register_count;
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while (register_count)
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{
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record_buf_mem[(register_count * 2) - 1] = start_address;
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record_buf_mem[(register_count * 2) - 2] = 4;
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start_address = start_address + 4;
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register_count--;
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}
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record_buf[0] = ARM_SP_REGNUM;
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thumb_insn_r->reg_rec_count = 1;
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}
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else if (0x1E == opcode1)
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{
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/* BKPT insn. */
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/* Handle enhanced software breakpoint insn, BKPT. */
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/* CPSR is changed to be executed in ARM state, disabling normal
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interrupts, entering abort mode. */
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/* According to high vector configuration PC is set. */
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/* User hits breakpoint and type reverse, in that case, we need to go back with
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previous CPSR and Program Counter. */
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record_buf[0] = ARM_PS_REGNUM;
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record_buf[1] = ARM_LR_REGNUM;
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thumb_insn_r->reg_rec_count = 2;
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/* We need to save SPSR value, which is not yet done. */
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printf_unfiltered (_("Process record does not support instruction "
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"0x%0x at address %s.\n"),
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thumb_insn_r->arm_insn,
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paddress (thumb_insn_r->gdbarch,
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thumb_insn_r->this_addr));
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return -1;
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}
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else if ((0 == opcode) || (1 == opcode))
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{
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/* ADD(5), ADD(6). */
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/* ADR and ADD (SP plus immediate) */
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reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
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record_buf[0] = reg_src1;
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thumb_insn_r->reg_rec_count = 1;
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}
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else if (2 == opcode)
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else
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{
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/* ADD(7), SUB(4). */
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reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
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record_buf[0] = ARM_SP_REGNUM;
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thumb_insn_r->reg_rec_count = 1;
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/* Miscellaneous 16-bit instructions */
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uint32_t opcode2 = bits (thumb_insn_r->arm_insn, 8, 11);
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switch (opcode2)
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{
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case 6:
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/* SETEND and CPS */
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break;
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case 0:
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/* ADD/SUB (SP plus immediate) */
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reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
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record_buf[0] = ARM_SP_REGNUM;
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thumb_insn_r->reg_rec_count = 1;
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break;
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case 1: /* fall through */
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case 3: /* fall through */
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case 9: /* fall through */
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case 11:
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/* CBNZ, CBZ */
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return -1;
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break;
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case 2:
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/* SXTH, SXTB, UXTH, UXTB */
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record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2);
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thumb_insn_r->reg_rec_count = 1;
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break;
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case 4: /* fall through */
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case 5:
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/* PUSH. */
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register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
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regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
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while (register_bits)
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{
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if (register_bits & 0x00000001)
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register_count++;
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register_bits = register_bits >> 1;
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}
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start_address = u_regval - \
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(4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
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thumb_insn_r->mem_rec_count = register_count;
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while (register_count)
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{
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record_buf_mem[(register_count * 2) - 1] = start_address;
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record_buf_mem[(register_count * 2) - 2] = 4;
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start_address = start_address + 4;
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register_count--;
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}
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record_buf[0] = ARM_SP_REGNUM;
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thumb_insn_r->reg_rec_count = 1;
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break;
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case 10:
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/* REV, REV16, REVSH */
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return -1;
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break;
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case 12: /* fall through */
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case 13:
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/* POP. */
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register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
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while (register_bits)
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{
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if (register_bits & 0x00000001)
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record_buf[index++] = register_count;
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register_bits = register_bits >> 1;
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register_count++;
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}
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record_buf[index++] = ARM_PS_REGNUM;
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record_buf[index++] = ARM_SP_REGNUM;
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thumb_insn_r->reg_rec_count = index;
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break;
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case 0xe:
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/* BKPT insn. */
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/* Handle enhanced software breakpoint insn, BKPT. */
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/* CPSR is changed to be executed in ARM state, disabling normal
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interrupts, entering abort mode. */
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/* According to high vector configuration PC is set. */
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/* User hits breakpoint and type reverse, in that case, we need to go back with
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previous CPSR and Program Counter. */
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record_buf[0] = ARM_PS_REGNUM;
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record_buf[1] = ARM_LR_REGNUM;
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thumb_insn_r->reg_rec_count = 2;
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/* We need to save SPSR value, which is not yet done. */
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printf_unfiltered (_("Process record does not support instruction "
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"0x%0x at address %s.\n"),
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thumb_insn_r->arm_insn,
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paddress (thumb_insn_r->gdbarch,
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thumb_insn_r->this_addr));
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return -1;
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case 0xf:
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/* If-Then, and hints */
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break;
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default:
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return -1;
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};
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}
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REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
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@ -12819,12 +12865,12 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
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/* Load/store multiple instruction. */
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return thumb2_record_ld_st_multiple (thumb2_insn_r);
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}
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else if (!((op2 & 0x64) ^ 0x04))
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else if ((op2 & 0x64) == 0x4)
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{
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/* Load/store (dual/exclusive) and table branch instruction. */
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return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
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}
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else if (!((op2 & 0x20) ^ 0x20))
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else if ((op2 & 0x60) == 0x20)
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{
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/* Data-processing (shifted register). */
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return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
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@ -13058,6 +13104,111 @@ decode_insn (abstract_memory_reader &reader, insn_decode_record *arm_record,
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return ret;
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}
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#if GDB_SELF_TEST
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namespace selftests {
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/* Provide both 16-bit and 32-bit thumb instructions. */
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class instruction_reader_thumb : public abstract_memory_reader
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{
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public:
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template<size_t SIZE>
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instruction_reader_thumb (enum bfd_endian endian,
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const uint16_t (&insns)[SIZE])
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: m_endian (endian), m_insns (insns), m_insns_size (SIZE)
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{}
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bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len)
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{
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SELF_CHECK (len == 4 || len == 2);
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SELF_CHECK (memaddr % 2 == 0);
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SELF_CHECK ((memaddr / 2) < m_insns_size);
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store_unsigned_integer (buf, 2, m_endian, m_insns[memaddr / 2]);
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if (len == 4)
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{
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store_unsigned_integer (&buf[2], 2, m_endian,
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m_insns[memaddr / 2 + 1]);
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}
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return true;
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}
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private:
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enum bfd_endian m_endian;
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const uint16_t *m_insns;
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size_t m_insns_size;
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};
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static void
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arm_record_test (void)
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{
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struct gdbarch_info info;
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gdbarch_info_init (&info);
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info.bfd_arch_info = bfd_scan_arch ("arm");
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struct gdbarch *gdbarch = gdbarch_find_by_info (info);
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SELF_CHECK (gdbarch != NULL);
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/* 16-bit Thumb instructions. */
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{
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insn_decode_record arm_record;
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memset (&arm_record, 0, sizeof (insn_decode_record));
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arm_record.gdbarch = gdbarch;
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static const uint16_t insns[] = {
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/* db b2 uxtb r3, r3 */
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0xb2db,
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/* cd 58 ldr r5, [r1, r3] */
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0x58cd,
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};
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enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch);
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instruction_reader_thumb reader (endian, insns);
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int ret = decode_insn (reader, &arm_record, THUMB_RECORD,
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THUMB_INSN_SIZE_BYTES);
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SELF_CHECK (ret == 0);
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SELF_CHECK (arm_record.mem_rec_count == 0);
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SELF_CHECK (arm_record.reg_rec_count == 1);
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SELF_CHECK (arm_record.arm_regs[0] == 3);
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arm_record.this_addr += 2;
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ret = decode_insn (reader, &arm_record, THUMB_RECORD,
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THUMB_INSN_SIZE_BYTES);
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SELF_CHECK (ret == 0);
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SELF_CHECK (arm_record.mem_rec_count == 0);
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SELF_CHECK (arm_record.reg_rec_count == 1);
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SELF_CHECK (arm_record.arm_regs[0] == 5);
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}
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/* 32-bit Thumb-2 instructions. */
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{
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insn_decode_record arm_record;
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memset (&arm_record, 0, sizeof (insn_decode_record));
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arm_record.gdbarch = gdbarch;
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static const uint16_t insns[] = {
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/* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */
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0xee1d, 0x7f70,
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};
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enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch);
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instruction_reader_thumb reader (endian, insns);
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int ret = decode_insn (reader, &arm_record, THUMB2_RECORD,
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THUMB2_INSN_SIZE_BYTES);
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SELF_CHECK (ret == 0);
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SELF_CHECK (arm_record.mem_rec_count == 0);
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SELF_CHECK (arm_record.reg_rec_count == 1);
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SELF_CHECK (arm_record.arm_regs[0] == 7);
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}
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}
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} // namespace selftests
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#endif /* GDB_SELF_TEST */
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/* Cleans up local record registers and memory allocations. */
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