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[ARM] Add support for M-profile MVE extension
This patch adds support for the M-profile MVE extension, which includes the
following:
- New M-profile XML feature m-profile-mve
- MVE vector predication status and control register (VPR)
- p0 pseudo register (contained in the VPR)
- q0 ~ q7 pseudo vector registers
- New feature bits
- Documentation update
Pseudo register p0 is the least significant bits of vpr and can be accessed
as $p0 or displayed through $vpr. For more information about the register
layout, please refer to [1].
The q0 ~ q7 registers map back to the d0 ~ d15 registers, two d registers
per q register.
The register dump looks like this:
(gdb) info reg all
r0 0x0 0
r1 0x0 0
r2 0x0 0
r3 0x0 0
r4 0x0 0
r5 0x0 0
r6 0x0 0
r7 0x0 0
r8 0x0 0
r9 0x0 0
r10 0x0 0
r11 0x0 0
r12 0x0 0
sp 0x0 0x0 <__Vectors>
lr 0xffffffff -1
pc 0xd0c 0xd0c <Reset_Handler>
xpsr 0x1000000 16777216
d0 0 (raw 0x0000000000000000)
d1 0 (raw 0x0000000000000000)
d2 0 (raw 0x0000000000000000)
d3 0 (raw 0x0000000000000000)
d4 0 (raw 0x0000000000000000)
d5 0 (raw 0x0000000000000000)
d6 0 (raw 0x0000000000000000)
d7 0 (raw 0x0000000000000000)
d8 0 (raw 0x0000000000000000)
d9 0 (raw 0x0000000000000000)
d10 0 (raw 0x0000000000000000)
d11 0 (raw 0x0000000000000000)
d12 0 (raw 0x0000000000000000)
d13 0 (raw 0x0000000000000000)
d14 0 (raw 0x0000000000000000)
d15 0 (raw 0x0000000000000000)
fpscr 0x0 0
vpr 0x0 [ P0=0 MASK01=0 MASK23=0 ]
s0 0 (raw 0x00000000)
s1 0 (raw 0x00000000)
s2 0 (raw 0x00000000)
s3 0 (raw 0x00000000)
s4 0 (raw 0x00000000)
s5 0 (raw 0x00000000)
s6 0 (raw 0x00000000)
s7 0 (raw 0x00000000)
s8 0 (raw 0x00000000)
s9 0 (raw 0x00000000)
s10 0 (raw 0x00000000)
s11 0 (raw 0x00000000)
s12 0 (raw 0x00000000)
s13 0 (raw 0x00000000)
s14 0 (raw 0x00000000)
s15 0 (raw 0x00000000)
s16 0 (raw 0x00000000)
s17 0 (raw 0x00000000)
s18 0 (raw 0x00000000)
s19 0 (raw 0x00000000)
s20 0 (raw 0x00000000)
s21 0 (raw 0x00000000)
s22 0 (raw 0x00000000)
s23 0 (raw 0x00000000)
s24 0 (raw 0x00000000)
s25 0 (raw 0x00000000)
s26 0 (raw 0x00000000)
s27 0 (raw 0x00000000)
s28 0 (raw 0x00000000)
s29 0 (raw 0x00000000)
s30 0 (raw 0x00000000)
s31 0 (raw 0x00000000)
q0 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q1 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q2 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q3 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q4 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q5 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q6 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q7 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
p0 0x0 0
Built and regtested with a simulator.
[1] https://developer.arm.com/documentation/ddi0553/bn
Co-Authored-By: Luis Machado <luis.machado@linaro.org>
This commit is contained in:
Srinath Parvathaneni
committed by
Luis Machado
Luis Machado
parent
ecbf5d4f9b
commit
ae66a8f19e
4
gdb/NEWS
4
gdb/NEWS
@ -152,6 +152,10 @@ maint show internal-warning backtrace
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registers of a target. The precise requirements of this register
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feature are documented in the GDB manual.
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* For ARM targets, the "org.gnu.gdb.arm.m-profile-mve" feature is now
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supported by GDB and describes a new VPR register from the ARM MVE
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(Helium) extension. See the GDB manual for more information.
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* TUI improvements
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** TUI windows now support mouse actions. The mouse wheel scrolls
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@ -27,6 +27,7 @@
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#include "../features/arm/xscale-iwmmxt.c"
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#include "../features/arm/arm-m-profile.c"
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#include "../features/arm/arm-m-profile-with-fpa.c"
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#include "../features/arm/arm-m-profile-mve.c"
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/* See arm.h. */
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@ -439,6 +440,12 @@ arm_create_mprofile_target_description (arm_m_profile_type m_type)
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regnum = create_feature_arm_arm_m_profile_with_fpa (tdesc, regnum);
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break;
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case ARM_M_TYPE_MVE:
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regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
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regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum);
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regnum = create_feature_arm_arm_m_profile_mve (tdesc, regnum);
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break;
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default:
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error (_("Invalid Arm M type: %d"), m_type);
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}
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@ -59,6 +59,8 @@ enum gdb_regnum {
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/* Register count constants. */
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enum arm_register_counts {
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/* Number of Q registers for MVE. */
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ARM_MVE_NUM_Q_REGS = 8,
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/* Number of argument registers. */
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ARM_NUM_ARG_REGS = 4,
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/* Number of floating point argument registers. */
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@ -89,6 +91,7 @@ enum arm_m_profile_type {
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ARM_M_TYPE_M_PROFILE,
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ARM_M_TYPE_VFP_D16,
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ARM_M_TYPE_WITH_FPA,
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ARM_M_TYPE_MVE,
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ARM_M_TYPE_INVALID
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};
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140
gdb/arm-tdep.c
140
gdb/arm-tdep.c
@ -4133,7 +4133,8 @@ is_q_pseudo (struct gdbarch *gdbarch, int regnum)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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/* Q pseudo registers are available for NEON (Q0~Q15). */
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/* Q pseudo registers are available for both NEON (Q0~Q15) and
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MVE (Q0~Q7) features. */
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if (tdep->have_q_pseudos
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&& regnum >= tdep->q_pseudo_base
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&& regnum < (tdep->q_pseudo_base + tdep->q_pseudo_count))
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@ -4161,6 +4162,25 @@ is_s_pseudo (struct gdbarch *gdbarch, int regnum)
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return false;
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}
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/* Return true if REGNUM is a MVE pseudo register (P0). Return false
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otherwise.
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REGNUM is the raw register number and not a pseudo-relative register
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number. */
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static bool
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is_mve_pseudo (struct gdbarch *gdbarch, int regnum)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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if (tdep->have_mve
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&& regnum >= tdep->mve_pseudo_base
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&& regnum < tdep->mve_pseudo_base + tdep->mve_pseudo_count)
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return true;
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return false;
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}
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/* Return the GDB type object for the "standard" data type of data in
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register N. */
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@ -4175,6 +4195,9 @@ arm_register_type (struct gdbarch *gdbarch, int regnum)
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if (is_q_pseudo (gdbarch, regnum))
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return arm_neon_quad_type (gdbarch);
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if (is_mve_pseudo (gdbarch, regnum))
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return builtin_type (gdbarch)->builtin_int16;
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/* If the target description has register information, we are only
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in this function so that we can override the types of
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double-precision registers for NEON. */
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@ -8612,6 +8635,9 @@ arm_register_name (struct gdbarch *gdbarch, int i)
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return q_pseudo_names[i - tdep->q_pseudo_base];
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}
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if (is_mve_pseudo (gdbarch, i))
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return "p0";
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if (i >= ARRAY_SIZE (arm_register_names))
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/* These registers are only supported on targets which supply
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an XML description. */
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@ -8745,6 +8771,19 @@ arm_neon_quad_read (struct gdbarch *gdbarch, readable_regcache *regcache,
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return REG_VALID;
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}
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/* Read the contents of the MVE pseudo register REGNUM and store it
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in BUF. */
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static enum register_status
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arm_mve_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache,
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int regnum, gdb_byte *buf)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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/* P0 is the first 16 bits of VPR. */
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return regcache->raw_read_part (tdep->mve_vpr_regnum, 0, 2, buf);
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}
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static enum register_status
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arm_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache,
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int regnum, gdb_byte *buf)
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@ -8764,6 +8803,8 @@ arm_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache,
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return arm_neon_quad_read (gdbarch, regcache,
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regnum - tdep->q_pseudo_base, buf);
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}
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else if (is_mve_pseudo (gdbarch, regnum))
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return arm_mve_pseudo_read (gdbarch, regcache, regnum, buf);
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else
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{
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enum register_status status;
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@ -8818,6 +8859,18 @@ arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache,
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regcache->raw_write (double_regnum + 1, buf + offset);
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}
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/* Store the contents of BUF to the MVE pseudo register REGNUM. */
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static void
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arm_mve_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
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int regnum, const gdb_byte *buf)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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/* P0 is the first 16 bits of VPR. */
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regcache->raw_write_part (tdep->mve_vpr_regnum, 0, 2, buf);
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}
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static void
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arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
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int regnum, const gdb_byte *buf)
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@ -8837,6 +8890,8 @@ arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
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arm_neon_quad_write (gdbarch, regcache,
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regnum - tdep->q_pseudo_base, buf);
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}
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else if (is_mve_pseudo (gdbarch, regnum))
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arm_mve_pseudo_write (gdbarch, regcache, regnum, buf);
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else
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{
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regnum -= tdep->s_pseudo_base;
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@ -8935,6 +8990,11 @@ arm_register_g_packet_guesses (struct gdbarch *gdbarch)
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register_remote_g_packet_guess (gdbarch,
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ARM_CORE_REGS_SIZE + ARM_VFP2_REGS_SIZE,
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tdesc);
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/* M-profile plus MVE. */
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tdesc = arm_read_mprofile_description (ARM_M_TYPE_MVE);
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register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE
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+ ARM_VFP2_REGS_SIZE
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+ ARM_INT_REGISTER_SIZE, tdesc);
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}
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/* Otherwise we don't have a useful guess. */
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@ -8991,6 +9051,9 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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bool have_neon = false;
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bool have_fpa_registers = true;
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const struct target_desc *tdesc = info.target_desc;
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bool have_vfp = false;
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bool have_mve = false;
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int mve_vpr_regnum = -1;
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int register_count = ARM_NUM_REGS;
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/* If we have an object to base this architecture on, try to determine
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@ -9106,6 +9169,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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if (!tdesc_has_registers (tdesc)
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&& (attr_arch == TAG_CPU_ARCH_V6_M
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|| attr_arch == TAG_CPU_ARCH_V6S_M
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|| attr_arch == TAG_CPU_ARCH_V8_1M_MAIN
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|| attr_profile == 'M'))
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is_m = true;
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#endif
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@ -9275,6 +9339,8 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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if (!valid_p)
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return NULL;
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have_vfp = true;
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if (tdesc_unnumbered_register (feature, "s0") == 0)
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have_s_pseudos = true;
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@ -9296,8 +9362,41 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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the default type. */
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if (tdesc_unnumbered_register (feature, "q0") == 0)
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have_q_pseudos = true;
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}
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}
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have_neon = true;
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/* Check for MVE after all the checks for GPR's, VFP and Neon.
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MVE (Helium) is an M-profile extension. */
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if (is_m)
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{
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/* Do we have the MVE feature? */
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feature = tdesc_find_feature (tdesc,"org.gnu.gdb.arm.m-profile-mve");
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if (feature != nullptr)
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{
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/* If we have MVE, we must always have the VPR register. */
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valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
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register_count, "vpr");
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if (!valid_p)
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{
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warning (_("MVE feature is missing required register vpr."));
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return nullptr;
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}
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have_mve = true;
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mve_vpr_regnum = register_count;
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register_count++;
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/* We can't have Q pseudo registers available here, as that
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would mean we have NEON features, and that is only available
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on A and R profiles. */
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gdb_assert (!have_q_pseudos);
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/* Given we have a M-profile target description, if MVE is
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enabled and there are VFP registers, we should have Q
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pseudo registers (Q0 ~ Q7). */
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if (have_vfp)
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have_q_pseudos = true;
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}
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}
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}
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@ -9349,6 +9448,13 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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tdep->have_q_pseudos = have_q_pseudos;
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tdep->have_neon = have_neon;
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/* Adjust the MVE feature settings. */
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if (have_mve)
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{
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tdep->have_mve = true;
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tdep->mve_vpr_regnum = mve_vpr_regnum;
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}
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arm_register_g_packet_guesses (gdbarch);
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/* Breakpoints. */
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@ -9530,21 +9636,39 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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}
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/* Initialize the pseudo register data. */
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int num_pseudos = 0;
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if (tdep->have_s_pseudos)
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{
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/* VFP single precision pseudo registers (S0~S31). */
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tdep->s_pseudo_base = register_count;
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tdep->s_pseudo_count = 32;
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int num_pseudos = tdep->s_pseudo_count;
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num_pseudos += tdep->s_pseudo_count;
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if (tdep->have_q_pseudos)
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{
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/* NEON quad precision pseudo registers (Q0~Q15). */
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tdep->q_pseudo_base = register_count + num_pseudos;
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tdep->q_pseudo_count = 16;
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if (have_neon)
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tdep->q_pseudo_count = 16;
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else if (have_mve)
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tdep->q_pseudo_count = ARM_MVE_NUM_Q_REGS;
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num_pseudos += tdep->q_pseudo_count;
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}
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}
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/* Do we have any MVE pseudo registers? */
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if (have_mve)
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{
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tdep->mve_pseudo_base = register_count + num_pseudos;
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tdep->mve_pseudo_count = 1;
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num_pseudos += tdep->mve_pseudo_count;
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}
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/* Set some pseudo register hooks, if we have pseudo registers. */
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if (tdep->have_s_pseudos || have_mve)
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{
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set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos);
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set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read);
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set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write);
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@ -9595,6 +9719,14 @@ arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
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(int) tdep->q_pseudo_count);
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fprintf_unfiltered (file, _("arm_dump_tdep: have_neon = %i\n"),
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(int) tdep->have_neon);
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fprintf_unfiltered (file, _("arm_dump_tdep: have_mve = %s\n"),
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tdep->have_mve? "yes" : "no");
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fprintf_unfiltered (file, _("arm_dump_tdep: mve_vpr_regnum = %i\n"),
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tdep->mve_vpr_regnum);
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fprintf_unfiltered (file, _("arm_dump_tdep: mve_pseudo_base = %i\n"),
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tdep->mve_pseudo_base);
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fprintf_unfiltered (file, _("arm_dump_tdep: mve_pseudo_count = %i\n"),
|
||||
tdep->mve_pseudo_count);
|
||||
fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx\n"),
|
||||
(unsigned long) tdep->lowest_pc);
|
||||
}
|
||||
|
||||
@ -114,6 +114,11 @@ struct gdbarch_tdep
|
||||
registers. */
|
||||
bool have_neon; /* Do we have a NEON unit? */
|
||||
|
||||
bool have_mve; /* Do we have a MVE extension? */
|
||||
int mve_vpr_regnum; /* MVE VPR register number. */
|
||||
int mve_pseudo_base; /* Number of the first MVE pseudo register. */
|
||||
int mve_pseudo_count; /* Total number of MVE pseudo registers. */
|
||||
|
||||
bool is_m; /* Does the target follow the "M" profile. */
|
||||
CORE_ADDR lowest_pc; /* Lowest address at which instructions
|
||||
will appear. */
|
||||
|
||||
@ -46212,6 +46212,17 @@ and @samp{xpsr}.
|
||||
The @samp{org.gnu.gdb.arm.fpa} feature is optional. If present, it
|
||||
should contain registers @samp{f0} through @samp{f7} and @samp{fps}.
|
||||
|
||||
The @samp{org.gnu.gdb.arm.m-profile-mve} feature is optional. If present, it
|
||||
must contain register @samp{vpr}.
|
||||
|
||||
If the @samp{org.gnu.gdb.arm.m-profile-mve} feature is available, @value{GDBN}
|
||||
will synthesize the @samp{p0} pseudo register from @samp{vpr} contents.
|
||||
|
||||
If the @samp{org.gnu.gdb.arm.vfp} feature is available alongside the
|
||||
@samp{org.gnu.gdb.arm.m-profile-mve} feature, @value{GDBN} will
|
||||
synthesize the @samp{q} pseudo registers from @samp{d} register
|
||||
contents.
|
||||
|
||||
The @samp{org.gnu.gdb.xscale.iwmmxt} feature is optional. If present,
|
||||
it should contain at least registers @samp{wR0} through @samp{wR15} and
|
||||
@samp{wCGR0} through @samp{wCGR3}. The @samp{wCID}, @samp{wCon},
|
||||
|
||||
@ -203,6 +203,7 @@ FEATURE_XMLFILES = aarch64-core.xml \
|
||||
arm/arm-core.xml \
|
||||
arm/arm-fpa.xml \
|
||||
arm/arm-m-profile.xml \
|
||||
arm/arm-m-profile-mve.xml \
|
||||
arm/arm-m-profile-with-fpa.xml \
|
||||
arm/arm-vfpv2.xml \
|
||||
arm/arm-vfpv3.xml \
|
||||
|
||||
20
gdb/features/arm/arm-m-profile-mve.c
Normal file
20
gdb/features/arm/arm-m-profile-mve.c
Normal file
@ -0,0 +1,20 @@
|
||||
/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
|
||||
Original: arm-m-profile-mve.xml */
|
||||
|
||||
#include "gdbsupport/tdesc.h"
|
||||
|
||||
static int
|
||||
create_feature_arm_arm_m_profile_mve (struct target_desc *result, long regnum)
|
||||
{
|
||||
struct tdesc_feature *feature;
|
||||
|
||||
feature = tdesc_create_feature (result, "org.gnu.gdb.arm.m-profile-mve");
|
||||
tdesc_type_with_fields *type_with_fields;
|
||||
type_with_fields = tdesc_create_flags (feature, "vpr_reg", 4);
|
||||
tdesc_add_bitfield (type_with_fields, "P0", 0, 15);
|
||||
tdesc_add_bitfield (type_with_fields, "MASK01", 16, 19);
|
||||
tdesc_add_bitfield (type_with_fields, "MASK23", 20, 23);
|
||||
|
||||
tdesc_create_reg (feature, "vpr", regnum++, 1, NULL, 32, "vpr_reg");
|
||||
return regnum;
|
||||
}
|
||||
19
gdb/features/arm/arm-m-profile-mve.xml
Normal file
19
gdb/features/arm/arm-m-profile-mve.xml
Normal file
@ -0,0 +1,19 @@
|
||||
<?xml version="1.0"?>
|
||||
<!-- Copyright (C) 2021 Free Software Foundation, Inc.
|
||||
|
||||
Copying and distribution of this file, with or without modification,
|
||||
are permitted in any medium without royalty provided the copyright
|
||||
notice and this notice are preserved. -->
|
||||
|
||||
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
|
||||
<feature name="org.gnu.gdb.arm.m-profile-mve">
|
||||
<flags id="vpr_reg" size="4">
|
||||
<!-- ARMv8.1-M and MVE: Unprivileged and privileged Access. -->
|
||||
<field name="P0" start="0" end="15"/>
|
||||
<!-- ARMv8.1-M: Privileged Access only. -->
|
||||
<field name="MASK01" start="16" end="19"/>
|
||||
<!-- ARMv8.1-M: Privileged Access only. -->
|
||||
<field name="MASK23" start="20" end="23"/>
|
||||
</flags>
|
||||
<reg name="vpr" bitsize="32" type="vpr_reg"/>
|
||||
</feature>
|
||||
Reference in New Issue
Block a user