aarch64: Add Armv8.8-A system registers

Armv8.8-A defines two new system registers: allint and icc_nmiar1_el1.
Both of them were previously unmapped.  allint supports a 0/1 immediate.
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ALLINT--All-Interrupt-Mask-Bit?lang=en]
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ICC-NMIAR1-EL1--Interrupt-Controller-Non-maskable-Interrupt-Acknowledge-Register-1?lang=en]

opcodes/
	* aarch64-opc.c (SR_V8_8): New macro.
	(aarch64_sys_regs): Add allint and icc_nmiar1_el1.
	(aarch64_pstatefields): Add allint.

gas/
	* testsuite/gas/aarch64/armv8_8-a-sysregs.s,
	* testsuite/gas/aarch64/armv8_8-a-sysregs.d: New test.
	* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.s,
	* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.l,
	* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.d: New test.

gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.d

@@ -0,0 +1 @@
+#error_output: armv8_8-a-sysregs-invalid.l

gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.l

@@ -0,0 +1,6 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 2 -- `msr allint,#-1'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 2 -- `msr allint,#2'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 2 -- `msr allint,#15'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 2 -- `msr allint,#0x100000000'
+[^:]*:[0-9]+: Warning: specified register cannot be written to at operand 1 -- `msr icc_nmiar1_el1,x0'

gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.s

@@ -0,0 +1,8 @@
+	.arch	armv8.8-a
+
+	msr	allint, #-1
+	msr	allint, #2
+	msr	allint, #15
+	msr	allint, #0x100000000
+
+	msr	icc_nmiar1_el1, x0

gas/testsuite/gas/aarch64/armv8_8-a-sysregs.d

@@ -0,0 +1,19 @@
+#as: -march=armv8.8-a
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+:\s+d5184300 	msr	allint, x0
+[^:]+:\s+d518430f 	msr	allint, x15
+[^:]+:\s+d518431e 	msr	allint, x30
+[^:]+:\s+d518431f 	msr	allint, xzr
+[^:]+:\s+d5384300 	mrs	x0, allint
+[^:]+:\s+d5384310 	mrs	x16, allint
+[^:]+:\s+d538431e 	mrs	x30, allint
+[^:]+:\s+d501401f 	msr	allint, #0x0
+[^:]+:\s+d501411f 	msr	allint, #0x1
+[^:]+:\s+d501421f 	msr	s0_1_c4_c2_0, xzr
+[^:]+:\s+d538c9a0 	mrs	x0, icc_nmiar1_el1

gas/testsuite/gas/aarch64/armv8_8-a-sysregs.s

@@ -0,0 +1,12 @@
+	msr	allint, x0
+	MSR	ALLINT, X15
+	msr	allint, x30
+	msr	allint, xzr
+	mrs	x0, allint
+	mrs	X16, ALLINT
+	mrs	x30, allint
+	msr	allint, #0
+	msr	allint, #1
+	.inst	0xd501421f
+
+	mrs	x0, icc_nmiar1_el1

opcodes/aarch64-opc.c

@@ -3975,6 +3975,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 #define SR_V8_4(n,e,f)	  SR_FEAT (n,e,f,V8_4)
 #define SR_V8_6(n,e,f)	  SR_FEAT (n,e,f,V8_6)
 #define SR_V8_7(n,e,f)	  SR_FEAT (n,e,f,V8_7)
+#define SR_V8_8(n,e,f)	  SR_FEAT (n,e,f,V8_8)
 /* Has no separate libopcodes feature flag, but separated out for clarity.  */
 #define SR_GIC(n,e,f)	  SR_CORE (n,e,f)
 /* Has no separate libopcodes feature flag, but separated out for clarity.  */
@@ -5000,6 +5001,9 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_V8_7 ("pmsnevfr_el1",      CPENC (3,0,C9,C9,1),    0),
   SR_V8_7 ("hcrx_el2",          CPENC (3,4,C1,C2,2),    0),
 
+  SR_V8_8 ("allint",            CPENC (3,0,C4,C3,0),    0),
+  SR_V8_8 ("icc_nmiar1_el1",    CPENC (3,0,C12,C9,5),   F_REG_READ),
+
   { 0, CPENC (0,0,0,0,0), 0, 0 }
 };
 
@@ -5032,6 +5036,7 @@ const aarch64_sys_reg aarch64_pstatefields [] =
 				| F_REG_MAX_VALUE (1)),
   SR_SME  ("svcrsmza",	  0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x6,0x1)
 				| F_REG_MAX_VALUE (1)),
+  SR_V8_8 ("allint",	  0x08,	F_REG_MAX_VALUE (1)),
   { 0,	  CPENC (0,0,0,0,0), 0, 0 },
 };