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gas: blackfin: fix DBG/DBGCMPLX insn encoding

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Some extended registers when given to the DBG/DBGCMPLX pseudo insns are
not encoded properly.  So fix them, fix the display of them when being
disassembled, and add testcases.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
2010-09-22 21:26:13 +00:00
parent efda024297
commit a01eda858f
8 changed files with 193 additions and 3 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2010-09-22 Robin Getz <robin.getz@analog.com>
* config/bfin-parse.y (DBG): Fix regno encoding.
(DBGCMPLX): Likewise.
2010-09-22 Robin Getz <robin.getz@analog.com>
* config/bfin-lex.l: Accept multibyte chars in symbol names.

4
gas/config/bfin-parse.y
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@ -3578,7 +3578,7 @@ asm_1:
| DBG REG
{
notethat ("pseudoDEBUG: DBG allregs\n");
$$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
$$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, ($2.regno & CLASS_MASK) >> 4);
}
| DBGCMPLX LPAREN REG RPAREN
@ -3586,7 +3586,7 @@ asm_1:
if (!IS_DREG ($3))
return yyerror ("Dregs expected");
notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
$$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
$$ = bfin_gen_pseudodbg (3, 6, ($3.regno & CODE_MASK) >> 4);
}
| DBGHALT

5
gas/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2010-09-22 Robin Getz <robin.getz@analog.com>
* gas/bfin/pseudo.d, gas/bfin/pseudo.s: New test.
* gas/bfin/bfin.exp: Add new "pseudo" test.
2010-09-22 Mike Frysinger <vapier@gentoo.org>
* gas/bfin/parallel2.d, gas/bfin/parallel3.d, gas/bfin/shift.d,

1
gas/testsuite/gas/bfin/bfin.exp
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@ -31,6 +31,7 @@ if [istarget bfin*-*-*] {
run_dump_test "parallel2"
run_dump_test "parallel3"
run_dump_test "parallel4"
run_dump_test "pseudo"
run_dump_test "reloc"
run_list_test "resource_conflict" ""
run_dump_test "shift"

82
gas/testsuite/gas/bfin/pseudo.d Normal file
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@ -0,0 +1,82 @@
#objdump: -dr
#name: pseudo
.*: +file format .*
Disassembly of section .text:
00000000 <debug>:
0: 00 f8 DBG R0;
2: 01 f8 DBG R1;
4: 02 f8 DBG R2;
6: 03 f8 DBG R3;
8: 04 f8 DBG R4;
a: 05 f8 DBG R5;
c: 06 f8 DBG R6;
e: 07 f8 DBG R7;
10: 08 f8 DBG P0;
12: 09 f8 DBG P1;
14: 0a f8 DBG P2;
16: 0b f8 DBG P3;
18: 0c f8 DBG P4;
1a: 0d f8 DBG P5;
1c: 0e f8 DBG SP;
1e: 0f f8 DBG FP;
20: 10 f8 DBG I0;
22: 11 f8 DBG I1;
24: 12 f8 DBG I2;
26: 13 f8 DBG I3;
28: 14 f8 DBG M0;
2a: 15 f8 DBG M1;
2c: 16 f8 DBG M2;
2e: 17 f8 DBG M3;
30: 18 f8 DBG B0;
32: 19 f8 DBG B1;
34: 1a f8 DBG B2;
36: 1b f8 DBG B3;
38: 1c f8 DBG L0;
3a: 1d f8 DBG L1;
3c: 1e f8 DBG L2;
3e: 1f f8 DBG L3;
40: 20 f8 DBG A0.X;
42: 21 f8 DBG A0.W;
44: 22 f8 DBG A1.X;
46: 23 f8 DBG A1.W;
48: 26 f8 DBG ASTAT;
4a: 27 f8 DBG RETS;
4c: 30 f8 DBG LC0;
4e: 31 f8 DBG LT0;
50: 32 f8 DBG LB0;
52: 33 f8 DBG LC1;
54: 34 f8 DBG LT1;
56: 35 f8 DBG LB1;
58: 36 f8 DBG CYCLES;
5a: 37 f8 DBG CYCLES2;
5c: 38 f8 DBG USP;
5e: 39 f8 DBG SEQSTAT;
60: 3a f8 DBG SYSCFG;
62: 3b f8 DBG RETI;
64: 3c f8 DBG RETX;
66: 3d f8 DBG RETN;
68: 3e f8 DBG RETE;
6a: 3f f8 DBG EMUDAT;
0000006c <debug_assert>:
6c: 00 f0 00 00 DBGA \(R0.L, 0x0\);
70: 40 f0 10 00 DBGA \(R0.H, 0x10\);
74: 00 f0 00 02 DBGA \(R0.L, 0x200\);
78: 40 f0 00 30 DBGA \(R0.H, 0x3000\);
7c: 01 f0 01 00 DBGA \(R1.L, 0x1\);
80: 41 f0 01 10 DBGA \(R1.H, 0x1001\);
84: 01 f0 08 80 DBGA \(R1.L, 0x8008\);
88: 41 f0 00 c0 DBGA \(R1.H, 0xc000\);
8c: 02 f0 00 04 DBGA \(R2.L, 0x400\);
90: 42 f0 00 08 DBGA \(R2.H, 0x800\);
94: 02 f0 00 10 DBGA \(R2.L, 0x1000\);
98: 42 f0 00 20 DBGA \(R2.H, 0x2000\);
9c: 03 f0 ff ff DBGA \(R3.L, 0xffff\);
a0: 43 f0 ff 7f DBGA \(R3.H, 0x7fff\);
a4: 03 f0 ff 3f DBGA \(R3.L, 0x3fff\);
a8: 43 f0 ff 1f DBGA \(R3.H, 0x1fff\);
ac: 0b f0 ff ff DBGA \(P3.L, 0xffff\);
b0: 4b f0 9c ff DBGA \(P3.H, 0xff9c\);
b4: 0b f0 18 fc DBGA \(P3.L, 0xfc18\);
b8: 4b f0 01 e0 DBGA \(P3.H, 0xe001\);

93
gas/testsuite/gas/bfin/pseudo.s Normal file
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@ -0,0 +1,93 @@
.text
.global debug
debug:
DBG R0;
DBG R1;
DBG R2;
DBG R3;
DBG R4;
DBG R5;
DBG R6;
DBG R7;
DBG P0;
DBG P1;
DBG P2;
DBG P3;
DBG P4;
DBG P5;
DBG SP;
DBG FP;
DBG I0;
DBG I1;
DBG I2;
DBG I3;
DBG M0;
DBG M1;
DBG M2;
DBG M3;
DBG B0;
DBG B1;
DBG B2;
DBG B3;
DBG L0;
DBG L1;
DBG L2;
DBG L3;
DBG A0.x;
DBG A0.w;
DBG A1.x;
DBG A1.w;
DBG ASTAT;
DBG RETS;
DBG LC0;
DBG LT0;
DBG LB0;
DBG LC1;
DBG LT1;
DBG LB1;
DBG CYCLES;
DBG CYCLES2;
DBG USP;
DBG SEQSTAT;
DBG SYSCFG;
DBG RETI;
DBG RETX;
DBG RETN;
DBG RETE;
DBG EMUDAT;
.global debug_assert
debug_assert:
DBGA(R0.L, 0x0000);
DBGA(R0.H, 0x0010);
DBGA(R0.L, 0x0200);
DBGA(R0.H, 0x3000);
DBGA(R1.L, 0x0001);
DBGA(R1.H, 0x1001);
DBGA(R1.L, 0x8008);
DBGA(R1.H, 0xC000);
DBGA(R2.L, 1024);
DBGA(R2.H, 2048);
DBGA(R2.L, 4096);
DBGA(R2.H, 8192);
DBGA(R3.L, 65535);
DBGA(R3.H, 32767);
DBGA(R3.L, 16383);
DBGA(R3.H, 8191);
DBGA(P3.L, -1);
DBGA(P3.H, -100);
DBGA(P3.L, -1000);
DBGA(P3.H, -8191);

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2010-09-22 Robin Getz <robin.getz@analog.com>
* bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
2010-09-22 Robin Getz <robin.getz@analog.com>
* bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.

2
opcodes/bfin-dis.c
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@ -4561,7 +4561,7 @@ decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
}
else if (fn == 0)
{
OUTS (outf, "DBG");
OUTS (outf, "DBG ");
OUTS (outf, allregs (reg, grp));
}
else if (fn == 1)