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[PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav, vrmlaldavh, vrmlalvh and vrmlsldavh
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vmlaldav, M_MNEM_vmlaldava, M_MNEM_vmlaldavx, M_MNEM_vmlaldavax, M_MNEM_vmlsldav, M_MNEM_vmlsldava, M_MNEM_vmlsldavx, M_MNEM_vmlsldavax, M_MNEM_vrmlaldavhx, M_MNEM_vrmlaldavhax, M_MNEM_vrmlsldavh, M_MNEM_vrmlsldavha, M_MNEM_vrmlsldavhx, M_MNEM_vrmlsldavhax): New instruction encodings. (NEON_SHAPE_DEF): New shape (mve_encode_rrqq): New encoding helper function. (do_mve_vmlaldav): New encoding function. (do_mve_vrmlaldavh): New encoding function. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vmlaldav-bad.d: New test. * testsuite/gas/arm/mve-vmlaldav-bad.l: New test. * testsuite/gas/arm/mve-vmlaldav-bad.s: New test. * testsuite/gas/arm/mve-vmlalv-bad.d: New test. * testsuite/gas/arm/mve-vmlalv-bad.l: New test. * testsuite/gas/arm/mve-vmlalv-bad.s: New test. * testsuite/gas/arm/mve-vmlsldav-bad.d: New test. * testsuite/gas/arm/mve-vmlsldav-bad.l: New test. * testsuite/gas/arm/mve-vmlsldav-bad.s: New test. * testsuite/gas/arm/mve-vrmlaldavh-bad.d: New test. * testsuite/gas/arm/mve-vrmlaldavh-bad.l: New test. * testsuite/gas/arm/mve-vrmlaldavh-bad.s: New test.
This commit is contained in:
Andre Vieira
@ -1,3 +1,29 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (M_MNEM_vmlaldav, M_MNEM_vmlaldava,
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M_MNEM_vmlaldavx, M_MNEM_vmlaldavax, M_MNEM_vmlsldav,
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M_MNEM_vmlsldava, M_MNEM_vmlsldavx, M_MNEM_vmlsldavax,
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M_MNEM_vrmlaldavhx, M_MNEM_vrmlaldavhax, M_MNEM_vrmlsldavh,
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M_MNEM_vrmlsldavha, M_MNEM_vrmlsldavhx, M_MNEM_vrmlsldavhax): New
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instruction encodings.
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(NEON_SHAPE_DEF): New shape
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(mve_encode_rrqq): New encoding helper function.
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(do_mve_vmlaldav): New encoding function.
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(do_mve_vrmlaldavh): New encoding function.
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(insns): Add entries for MVE mnemonics.
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* testsuite/gas/arm/mve-vmlaldav-bad.d: New test.
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* testsuite/gas/arm/mve-vmlaldav-bad.l: New test.
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* testsuite/gas/arm/mve-vmlaldav-bad.s: New test.
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* testsuite/gas/arm/mve-vmlalv-bad.d: New test.
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* testsuite/gas/arm/mve-vmlalv-bad.l: New test.
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* testsuite/gas/arm/mve-vmlalv-bad.s: New test.
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* testsuite/gas/arm/mve-vmlsldav-bad.d: New test.
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* testsuite/gas/arm/mve-vmlsldav-bad.l: New test.
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* testsuite/gas/arm/mve-vmlsldav-bad.s: New test.
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* testsuite/gas/arm/mve-vrmlaldavh-bad.d: New test.
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* testsuite/gas/arm/mve-vrmlaldavh-bad.l: New test.
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* testsuite/gas/arm/mve-vrmlaldavh-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (M_MNEM_vmaxv, M_MNEM_vmaxav, M_MNEM_vminv,
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@ -14167,6 +14167,20 @@ do_t_loloop (void)
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#define M_MNEM_vmaxav 0xeee00f00
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#define M_MNEM_vminv 0xeee20f80
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#define M_MNEM_vminav 0xeee00f80
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#define M_MNEM_vmlaldav 0xee800e00
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#define M_MNEM_vmlaldava 0xee800e20
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#define M_MNEM_vmlaldavx 0xee801e00
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#define M_MNEM_vmlaldavax 0xee801e20
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#define M_MNEM_vmlsldav 0xee800e01
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#define M_MNEM_vmlsldava 0xee800e21
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#define M_MNEM_vmlsldavx 0xee801e01
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#define M_MNEM_vmlsldavax 0xee801e21
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#define M_MNEM_vrmlaldavhx 0xee801f00
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#define M_MNEM_vrmlaldavhax 0xee801f20
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#define M_MNEM_vrmlsldavh 0xfe800e01
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#define M_MNEM_vrmlsldavha 0xfe800e21
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#define M_MNEM_vrmlsldavhx 0xfe801e01
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#define M_MNEM_vrmlsldavhax 0xfe801e21
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/* Neon instruction encoder helpers. */
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@ -14331,6 +14345,7 @@ NEON_ENC_TAB
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- a table used to drive neon_select_shape. */
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#define NEON_SHAPE_DEF \
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X(4, (R, R, Q, Q), QUAD), \
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X(4, (Q, R, R, I), QUAD), \
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X(4, (R, R, S, S), QUAD), \
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X(4, (S, S, R, R), QUAD), \
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@ -15956,6 +15971,21 @@ mve_encode_rq (unsigned bit28, unsigned size)
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inst.is_neon = 1;
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}
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static void
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mve_encode_rrqq (unsigned U, unsigned size)
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{
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constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
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inst.instruction |= U << 28;
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inst.instruction |= (inst.operands[1].reg >> 1) << 20;
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inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
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inst.instruction |= (size == 32) << 16;
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inst.instruction |= inst.operands[0].reg << 12;
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inst.instruction |= HI1 (inst.operands[2].reg) << 7;
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inst.instruction |= inst.operands[3].reg;
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inst.is_neon = 1;
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}
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/* Encode insns with bit pattern:
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|28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
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@ -17252,6 +17282,73 @@ do_mve_vmladav (void)
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inst.instruction |= (et.size == 32) << 16;
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}
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static void
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do_mve_vmlaldav (void)
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{
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enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL);
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struct neon_type_el et
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= neon_check_type (4, rs, N_EQK, N_EQK, N_EQK,
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N_S16 | N_S32 | N_U16 | N_U32 | N_KEY);
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if (et.type == NT_unsigned
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&& (inst.instruction == M_MNEM_vmlsldav
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|| inst.instruction == M_MNEM_vmlsldava
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|| inst.instruction == M_MNEM_vmlsldavx
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|| inst.instruction == M_MNEM_vmlsldavax))
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first_error (BAD_SIMD_TYPE);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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mve_encode_rrqq (et.type == NT_unsigned, et.size);
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}
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static void
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do_mve_vrmlaldavh (void)
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{
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struct neon_type_el et;
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if (inst.instruction == M_MNEM_vrmlsldavh
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|| inst.instruction == M_MNEM_vrmlsldavha
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|| inst.instruction == M_MNEM_vrmlsldavhx
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|| inst.instruction == M_MNEM_vrmlsldavhax)
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{
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et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
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if (inst.operands[1].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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}
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else
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{
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if (inst.instruction == M_MNEM_vrmlaldavhx
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|| inst.instruction == M_MNEM_vrmlaldavhax)
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et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
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else
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et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK,
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N_U32 | N_S32 | N_KEY);
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/* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
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with vmax/min instructions, making the use of SP in assembly really
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nonsensical, so instead of issuing a warning like we do for other uses
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of SP for the odd register operand we error out. */
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constraint (inst.operands[1].reg == REG_SP, BAD_SP);
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}
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/* Make sure we still check the second operand is an odd one and that PC is
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disallowed. This because we are parsing for any GPR operand, to be able
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to distinguish between giving a warning or an error for SP as described
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above. */
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constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
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constraint (inst.operands[1].reg == REG_PC, BAD_PC);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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mve_encode_rrqq (et.type == NT_unsigned, 0);
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}
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static void
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do_mve_vmaxnmv (void)
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{
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@ -24468,6 +24565,27 @@ static const struct asm_opcode insns[] =
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mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv),
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mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv),
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mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
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mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
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mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
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mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
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mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
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mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
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mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
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mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
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mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
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mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
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mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
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5
gas/testsuite/gas/arm/mve-vmlaldav-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vmlaldav-bad.d
Normal file
@ -0,0 +1,5 @@
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#name: Bad MVE VMLALDAV instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vmlaldav-bad.l
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.*: +file format .*arm.*
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62
gas/testsuite/gas/arm/mve-vmlaldav-bad.l
Normal file
62
gas/testsuite/gas/arm/mve-vmlaldav-bad.l
Normal file
@ -0,0 +1,62 @@
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[^:]*: Assembler messages:
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[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Error: bad type in SIMD instruction -- `vmlaldav.s64 r0,r1,q1,q2'
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[^:]*:16: Error: bad type in SIMD instruction -- `vmlaldav.f32 r0,r1,q1,q2'
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[^:]*:17: Error: bad type in SIMD instruction -- `vmlaldav.s8 r0,r1,q1,q2'
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[^:]*:18: Error: ARM register expected -- `vmlaldav.s16 r0,q1,q2'
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[^:]*:19: Error: bad type in SIMD instruction -- `vmlaldava.s64 r0,r1,q1,q2'
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[^:]*:20: Error: bad type in SIMD instruction -- `vmlaldava.f32 r0,r1,q1,q2'
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[^:]*:21: Error: bad type in SIMD instruction -- `vmlaldava.s8 r0,r1,q1,q2'
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[^:]*:22: Error: ARM register expected -- `vmlaldava.s16 r0,q1,q2'
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[^:]*:23: Error: bad type in SIMD instruction -- `vmlaldavx.s64 r0,r1,q1,q2'
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[^:]*:24: Error: bad type in SIMD instruction -- `vmlaldavx.f32 r0,r1,q1,q2'
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[^:]*:25: Error: bad type in SIMD instruction -- `vmlaldavx.s8 r0,r1,q1,q2'
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[^:]*:26: Error: ARM register expected -- `vmlaldavx.s16 r0,q1,q2'
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[^:]*:27: Error: bad type in SIMD instruction -- `vmlaldavax.s64 r0,r1,q1,q2'
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[^:]*:28: Error: bad type in SIMD instruction -- `vmlaldavax.f32 r0,r1,q1,q2'
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[^:]*:29: Error: bad type in SIMD instruction -- `vmlaldavax.s8 r0,r1,q1,q2'
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[^:]*:30: Error: ARM register expected -- `vmlaldavax.s16 r0,q1,q2'
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[^:]*:32: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
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[^:]*:33: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
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[^:]*:34: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
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[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavt.s16 r0,r1,q1,q2'
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[^:]*:37: Error: instruction missing MVE vector predication code -- `vmlaldav.s16 r0,r1,q1,q2'
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[^:]*:39: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
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[^:]*:40: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
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[^:]*:41: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
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[^:]*:42: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavat.s16 r0,r1,q1,q2'
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[^:]*:44: Error: instruction missing MVE vector predication code -- `vmlaldava.s16 r0,r1,q1,q2'
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[^:]*:46: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
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[^:]*:47: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
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[^:]*:48: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
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[^:]*:49: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavxt.s16 r0,r1,q1,q2'
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[^:]*:51: Error: instruction missing MVE vector predication code -- `vmlaldavx.s16 r0,r1,q1,q2'
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[^:]*:53: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
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[^:]*:54: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
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[^:]*:55: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
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[^:]*:56: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavaxt.s16 r0,r1,q1,q2'
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[^:]*:58: Error: instruction missing MVE vector predication code -- `vmlaldavax.s16 r0,r1,q1,q2'
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58
gas/testsuite/gas/arm/mve-vmlaldav-bad.s
Normal file
58
gas/testsuite/gas/arm/mve-vmlaldav-bad.s
Normal file
@ -0,0 +1,58 @@
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.macro cond, op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s16 r0, r1, q1, q2
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.endr
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.endm
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.syntax unified
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.thumb
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vmlaldav.s16 r0, sp, q1, q2
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cond vmlaldav
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cond vmlaldava
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cond vmlaldavx
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||||
cond vmlaldavax
|
||||
vmlaldav.s64 r0, r1, q1, q2
|
||||
vmlaldav.f32 r0, r1, q1, q2
|
||||
vmlaldav.s8 r0, r1, q1, q2
|
||||
vmlaldav.s16 r0, q1, q2
|
||||
vmlaldava.s64 r0, r1, q1, q2
|
||||
vmlaldava.f32 r0, r1, q1, q2
|
||||
vmlaldava.s8 r0, r1, q1, q2
|
||||
vmlaldava.s16 r0, q1, q2
|
||||
vmlaldavx.s64 r0, r1, q1, q2
|
||||
vmlaldavx.f32 r0, r1, q1, q2
|
||||
vmlaldavx.s8 r0, r1, q1, q2
|
||||
vmlaldavx.s16 r0, q1, q2
|
||||
vmlaldavax.s64 r0, r1, q1, q2
|
||||
vmlaldavax.f32 r0, r1, q1, q2
|
||||
vmlaldavax.s8 r0, r1, q1, q2
|
||||
vmlaldavax.s16 r0, q1, q2
|
||||
it eq
|
||||
vmlaldaveq.s16 r0, r1, q1, q2
|
||||
vmlaldaveq.s16 r0, r1, q1, q2
|
||||
vmlaldaveq.s16 r0, r1, q1, q2
|
||||
vmlaldavt.s16 r0, r1, q1, q2
|
||||
vpst
|
||||
vmlaldav.s16 r0, r1, q1, q2
|
||||
it eq
|
||||
vmlaldavaeq.s16 r0, r1, q1, q2
|
||||
vmlaldavaeq.s16 r0, r1, q1, q2
|
||||
vmlaldavaeq.s16 r0, r1, q1, q2
|
||||
vmlaldavat.s16 r0, r1, q1, q2
|
||||
vpst
|
||||
vmlaldava.s16 r0, r1, q1, q2
|
||||
it eq
|
||||
vmlaldavxeq.s16 r0, r1, q1, q2
|
||||
vmlaldavxeq.s16 r0, r1, q1, q2
|
||||
vmlaldavxeq.s16 r0, r1, q1, q2
|
||||
vmlaldavxt.s16 r0, r1, q1, q2
|
||||
vpst
|
||||
vmlaldavx.s16 r0, r1, q1, q2
|
||||
it eq
|
||||
vmlaldavaxeq.s16 r0, r1, q1, q2
|
||||
vmlaldavaxeq.s16 r0, r1, q1, q2
|
||||
vmlaldavaxeq.s16 r0, r1, q1, q2
|
||||
vmlaldavaxt.s16 r0, r1, q1, q2
|
||||
vpst
|
||||
vmlaldavax.s16 r0, r1, q1, q2
|
||||
5
gas/testsuite/gas/arm/mve-vmlalv-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vmlalv-bad.d
Normal file
@ -0,0 +1,5 @@
|
||||
#name: Bad MVE VMLADALV instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vmlalv-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
33
gas/testsuite/gas/arm/mve-vmlalv-bad.l
Normal file
33
gas/testsuite/gas/arm/mve-vmlalv-bad.l
Normal file
@ -0,0 +1,33 @@
|
||||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vmlalv.s64 r0,r1,q1,q2'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vmlalv.f32 r0,r1,q1,q2'
|
||||
[^:]*:14: Error: bad type in SIMD instruction -- `vmlalv.s8 r0,r1,q1,q2'
|
||||
[^:]*:15: Error: ARM register expected -- `vmlalv.s16 r0,q1,q2'
|
||||
[^:]*:16: Error: bad type in SIMD instruction -- `vmlalva.s64 r0,r1,q1,q2'
|
||||
[^:]*:17: Error: bad type in SIMD instruction -- `vmlalva.f32 r0,r1,q1,q2'
|
||||
[^:]*:18: Error: bad type in SIMD instruction -- `vmlalva.s8 r0,r1,q1,q2'
|
||||
[^:]*:19: Error: ARM register expected -- `vmlalva.s16 r0,q1,q2'
|
||||
[^:]*:20: Error: bad instruction `vmlalvx.s16 r0,r1,q1,q2'
|
||||
[^:]*:21: Error: bad instruction `vmlalvax.s16 r0,r1,q1,q2'
|
||||
[^:]*:23: Error: syntax error -- `vmlalveq.s16 r0,r1,q1,q2'
|
||||
[^:]*:24: Error: syntax error -- `vmlalveq.s16 r0,r1,q1,q2'
|
||||
[^:]*:25: Error: syntax error -- `vmlalveq.s16 r0,r1,q1,q2'
|
||||
[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vmlalvt.s16 r0,r1,q1,q2'
|
||||
[^:]*:28: Error: instruction missing MVE vector predication code -- `vmlalv.s16 r0,r1,q1,q2'
|
||||
[^:]*:30: Error: syntax error -- `vmlalvaeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:31: Error: syntax error -- `vmlalvaeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:32: Error: syntax error -- `vmlalvaeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vmlalvat.s16 r0,r1,q1,q2'
|
||||
[^:]*:35: Error: instruction missing MVE vector predication code -- `vmlalva.s16 r0,r1,q1,q2'
|
||||
35
gas/testsuite/gas/arm/mve-vmlalv-bad.s
Normal file
35
gas/testsuite/gas/arm/mve-vmlalv-bad.s
Normal file
@ -0,0 +1,35 @@
|
||||
.macro cond, op
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().s16 r0, r1, q1, q2
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
cond vmlalv
|
||||
cond vmlalva
|
||||
vmlalv.s64 r0, r1, q1, q2
|
||||
vmlalv.f32 r0, r1, q1, q2
|
||||
vmlalv.s8 r0, r1, q1, q2
|
||||
vmlalv.s16 r0, q1, q2
|
||||
vmlalva.s64 r0, r1, q1, q2
|
||||
vmlalva.f32 r0, r1, q1, q2
|
||||
vmlalva.s8 r0, r1, q1, q2
|
||||
vmlalva.s16 r0, q1, q2
|
||||
vmlalvx.s16 r0, r1, q1, q2
|
||||
vmlalvax.s16 r0, r1, q1, q2
|
||||
it eq
|
||||
vmlalveq.s16 r0, r1, q1, q2
|
||||
vmlalveq.s16 r0, r1, q1, q2
|
||||
vmlalveq.s16 r0, r1, q1, q2
|
||||
vmlalvt.s16 r0, r1, q1, q2
|
||||
vpst
|
||||
vmlalv.s16 r0, r1, q1, q2
|
||||
it eq
|
||||
vmlalvaeq.s16 r0, r1, q1, q2
|
||||
vmlalvaeq.s16 r0, r1, q1, q2
|
||||
vmlalvaeq.s16 r0, r1, q1, q2
|
||||
vmlalvat.s16 r0, r1, q1, q2
|
||||
vpst
|
||||
vmlalva.s16 r0, r1, q1, q2
|
||||
5
gas/testsuite/gas/arm/mve-vmlsldav-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vmlsldav-bad.d
Normal file
@ -0,0 +1,5 @@
|
||||
#name: Bad MVE VMLSLDAV instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vmlsldav-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
63
gas/testsuite/gas/arm/mve-vmlsldav-bad.l
Normal file
63
gas/testsuite/gas/arm/mve-vmlsldav-bad.l
Normal file
@ -0,0 +1,63 @@
|
||||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vmlsldav.u16 r0,r1,q1,q2'
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Error: bad type in SIMD instruction -- `vmlsldav.s64 r0,r1,q1,q2'
|
||||
[^:]*:17: Error: bad type in SIMD instruction -- `vmlsldav.f32 r0,r1,q1,q2'
|
||||
[^:]*:18: Error: bad type in SIMD instruction -- `vmlsldav.s8 r0,r1,q1,q2'
|
||||
[^:]*:19: Error: ARM register expected -- `vmlsldav.s16 r0,q1,q2'
|
||||
[^:]*:20: Error: bad type in SIMD instruction -- `vmlsldava.s64 r0,r1,q1,q2'
|
||||
[^:]*:21: Error: bad type in SIMD instruction -- `vmlsldava.f32 r0,r1,q1,q2'
|
||||
[^:]*:22: Error: bad type in SIMD instruction -- `vmlsldava.s8 r0,r1,q1,q2'
|
||||
[^:]*:23: Error: ARM register expected -- `vmlsldava.s16 r0,q1,q2'
|
||||
[^:]*:24: Error: bad type in SIMD instruction -- `vmlsldavx.s64 r0,r1,q1,q2'
|
||||
[^:]*:25: Error: bad type in SIMD instruction -- `vmlsldavx.f32 r0,r1,q1,q2'
|
||||
[^:]*:26: Error: bad type in SIMD instruction -- `vmlsldavx.s8 r0,r1,q1,q2'
|
||||
[^:]*:27: Error: ARM register expected -- `vmlsldavx.s16 r0,q1,q2'
|
||||
[^:]*:28: Error: bad type in SIMD instruction -- `vmlsldavax.s64 r0,r1,q1,q2'
|
||||
[^:]*:29: Error: bad type in SIMD instruction -- `vmlsldavax.f32 r0,r1,q1,q2'
|
||||
[^:]*:30: Error: bad type in SIMD instruction -- `vmlsldavax.s8 r0,r1,q1,q2'
|
||||
[^:]*:31: Error: ARM register expected -- `vmlsldavax.s16 r0,q1,q2'
|
||||
[^:]*:33: Error: syntax error -- `vmlsldaveq.s16 r0,r1,q1,q2'
|
||||
[^:]*:34: Error: syntax error -- `vmlsldaveq.s16 r0,r1,q1,q2'
|
||||
[^:]*:35: Error: syntax error -- `vmlsldaveq.s16 r0,r1,q1,q2'
|
||||
[^:]*:36: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsldavt.s16 r0,r1,q1,q2'
|
||||
[^:]*:38: Error: instruction missing MVE vector predication code -- `vmlsldav.s16 r0,r1,q1,q2'
|
||||
[^:]*:40: Error: syntax error -- `vmlsldavaeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:41: Error: syntax error -- `vmlsldavaeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:42: Error: syntax error -- `vmlsldavaeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsldavat.s16 r0,r1,q1,q2'
|
||||
[^:]*:45: Error: instruction missing MVE vector predication code -- `vmlsldava.s16 r0,r1,q1,q2'
|
||||
[^:]*:47: Error: syntax error -- `vmlsldavxeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:48: Error: syntax error -- `vmlsldavxeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:49: Error: syntax error -- `vmlsldavxeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:50: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsldavxt.s16 r0,r1,q1,q2'
|
||||
[^:]*:52: Error: instruction missing MVE vector predication code -- `vmlsldavx.s16 r0,r1,q1,q2'
|
||||
[^:]*:54: Error: syntax error -- `vmlsldavaxeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:55: Error: syntax error -- `vmlsldavaxeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:56: Error: syntax error -- `vmlsldavaxeq.s16 r0,r1,q1,q2'
|
||||
[^:]*:57: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsldavaxt.s16 r0,r1,q1,q2'
|
||||
[^:]*:59: Error: instruction missing MVE vector predication code -- `vmlsldavax.s16 r0,r1,q1,q2'
|
||||
60
gas/testsuite/gas/arm/mve-vmlsldav-bad.s
Normal file
60
gas/testsuite/gas/arm/mve-vmlsldav-bad.s
Normal file
@ -0,0 +1,60 @@
|
||||
.macro cond, op
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().s16 r0, r1, q1, q2
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vmlsldav.s16 r0, sp, q1, q2
|
||||
vmlsldav.u16 r0, r1, q1, q2
|
||||
cond vmlsldav
|
||||
cond vmlsldava
|
||||
cond vmlsldavx
|
||||
cond vmlsldavax
|
||||
vmlsldav.s64 r0, r1, q1, q2
|
||||
vmlsldav.f32 r0, r1, q1, q2
|
||||
vmlsldav.s8 r0, r1, q1, q2
|
||||
vmlsldav.s16 r0, q1, q2
|
||||
vmlsldava.s64 r0, r1, q1, q2
|
||||
vmlsldava.f32 r0, r1, q1, q2
|
||||
vmlsldava.s8 r0, r1, q1, q2
|
||||
vmlsldava.s16 r0, q1, q2
|
||||
vmlsldavx.s64 r0, r1, q1, q2
|
||||
vmlsldavx.f32 r0, r1, q1, q2
|
||||
vmlsldavx.s8 r0, r1, q1, q2
|
||||
vmlsldavx.s16 r0, q1, q2
|
||||
vmlsldavax.s64 r0, r1, q1, q2
|
||||
vmlsldavax.f32 r0, r1, q1, q2
|
||||
vmlsldavax.s8 r0, r1, q1, q2
|
||||
vmlsldavax.s16 r0, q1, q2
|
||||
it eq
|
||||
vmlsldaveq.s16 r0, r1, q1, q2
|
||||
vmlsldaveq.s16 r0, r1, q1, q2
|
||||
vmlsldaveq.s16 r0, r1, q1, q2
|
||||
vmlsldavt.s16 r0, r1, q1, q2
|
||||
vpst
|
||||
vmlsldav.s16 r0, r1, q1, q2
|
||||
it eq
|
||||
vmlsldavaeq.s16 r0, r1, q1, q2
|
||||
vmlsldavaeq.s16 r0, r1, q1, q2
|
||||
vmlsldavaeq.s16 r0, r1, q1, q2
|
||||
vmlsldavat.s16 r0, r1, q1, q2
|
||||
vpst
|
||||
vmlsldava.s16 r0, r1, q1, q2
|
||||
it eq
|
||||
vmlsldavxeq.s16 r0, r1, q1, q2
|
||||
vmlsldavxeq.s16 r0, r1, q1, q2
|
||||
vmlsldavxeq.s16 r0, r1, q1, q2
|
||||
vmlsldavxt.s16 r0, r1, q1, q2
|
||||
vpst
|
||||
vmlsldavx.s16 r0, r1, q1, q2
|
||||
it eq
|
||||
vmlsldavaxeq.s16 r0, r1, q1, q2
|
||||
vmlsldavaxeq.s16 r0, r1, q1, q2
|
||||
vmlsldavaxeq.s16 r0, r1, q1, q2
|
||||
vmlsldavaxt.s16 r0, r1, q1, q2
|
||||
vpst
|
||||
vmlsldavax.s16 r0, r1, q1, q2
|
||||
|
||||
5
gas/testsuite/gas/arm/mve-vrmlaldavh-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vrmlaldavh-bad.d
Normal file
@ -0,0 +1,5 @@
|
||||
#name: bad VRMLALDAVH, VRMLALVH and VRMLSLDAVH instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vrmlaldavh-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
171
gas/testsuite/gas/arm/mve-vrmlaldavh-bad.l
Normal file
171
gas/testsuite/gas/arm/mve-vrmlaldavh-bad.l
Normal file
@ -0,0 +1,171 @@
|
||||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Error: bad type in SIMD instruction -- `vrmlaldavh.s16 r0,r1,q2,q3'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vrmlaldavh.i32 r0,r1,q2,q3'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vrmlaldavha.s16 r0,r1,q2,q3'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrmlaldavha.i32 r0,r1,q2,q3'
|
||||
[^:]*:14: Error: bad type in SIMD instruction -- `vrmlalvh.s16 r0,r1,q2,q3'
|
||||
[^:]*:15: Error: bad type in SIMD instruction -- `vrmlalvh.i32 r0,r1,q2,q3'
|
||||
[^:]*:16: Error: bad type in SIMD instruction -- `vrmlalvha.s16 r0,r1,q2,q3'
|
||||
[^:]*:17: Error: bad type in SIMD instruction -- `vrmlalvha.i32 r0,r1,q2,q3'
|
||||
[^:]*:18: Error: bad type in SIMD instruction -- `vrmlaldavhx.u32 r0,r1,q2,q3'
|
||||
[^:]*:19: Error: bad type in SIMD instruction -- `vrmlaldavhax.u32 r0,r1,q2,q3'
|
||||
[^:]*:20: Error: bad type in SIMD instruction -- `vrmlaldavhx.i32 r0,r1,q2,q3'
|
||||
[^:]*:21: Error: bad type in SIMD instruction -- `vrmlaldavhax.i32 r0,r1,q2,q3'
|
||||
[^:]*:22: Error: bad type in SIMD instruction -- `vrmlsldavh.s16 r0,r1,q2,q3'
|
||||
[^:]*:23: Error: bad type in SIMD instruction -- `vrmlsldavh.u32 r0,r1,q2,q3'
|
||||
[^:]*:24: Error: bad type in SIMD instruction -- `vrmlsldavha.s16 r0,r1,q2,q3'
|
||||
[^:]*:25: Error: bad type in SIMD instruction -- `vrmlsldavha.u32 r0,r1,q2,q3'
|
||||
[^:]*:26: Error: bad type in SIMD instruction -- `vrmlsldavhx.s16 r0,r1,q2,q3'
|
||||
[^:]*:27: Error: bad type in SIMD instruction -- `vrmlsldavhx.u32 r0,r1,q2,q3'
|
||||
[^:]*:28: Error: bad type in SIMD instruction -- `vrmlsldavhax.s16 r0,r1,q2,q3'
|
||||
[^:]*:29: Error: bad type in SIMD instruction -- `vrmlsldavhax.u32 r0,r1,q2,q3'
|
||||
[^:]*:30: Error: Odd register not allowed here -- `vrmlaldavh.s32 r1,r1,q2,q3'
|
||||
[^:]*:31: Error: Even register not allowed here -- `vrmlaldavh.s32 r0,r0,q2,q3'
|
||||
[^:]*:32: Error: r13 not allowed here -- `vrmlaldavh.s32 r0,sp,q2,q3'
|
||||
[^:]*:33: Error: r15 not allowed here -- `vrmlaldavh.s32 r0,pc,q2,q3'
|
||||
[^:]*:34: Error: Odd register not allowed here -- `vrmlaldavha.s32 r1,r1,q2,q3'
|
||||
[^:]*:35: Error: Even register not allowed here -- `vrmlaldavha.s32 r0,r0,q2,q3'
|
||||
[^:]*:36: Error: r13 not allowed here -- `vrmlaldavha.s32 r0,sp,q2,q3'
|
||||
[^:]*:37: Error: r15 not allowed here -- `vrmlaldavha.s32 r0,pc,q2,q3'
|
||||
[^:]*:38: Error: Odd register not allowed here -- `vrmlaldavhx.s32 r1,r1,q2,q3'
|
||||
[^:]*:39: Error: Even register not allowed here -- `vrmlaldavhx.s32 r0,r0,q2,q3'
|
||||
[^:]*:40: Error: r13 not allowed here -- `vrmlaldavhx.s32 r0,sp,q2,q3'
|
||||
[^:]*:41: Error: r15 not allowed here -- `vrmlaldavhx.s32 r0,pc,q2,q3'
|
||||
[^:]*:42: Error: Odd register not allowed here -- `vrmlaldavhax.s32 r1,r1,q2,q3'
|
||||
[^:]*:43: Error: Even register not allowed here -- `vrmlaldavhax.s32 r0,r0,q2,q3'
|
||||
[^:]*:44: Error: r13 not allowed here -- `vrmlaldavhax.s32 r0,sp,q2,q3'
|
||||
[^:]*:45: Error: r15 not allowed here -- `vrmlaldavhax.s32 r0,pc,q2,q3'
|
||||
[^:]*:46: Error: Odd register not allowed here -- `vrmlalvh.s32 r1,r1,q2,q3'
|
||||
[^:]*:47: Error: Even register not allowed here -- `vrmlalvh.s32 r0,r0,q2,q3'
|
||||
[^:]*:48: Error: r13 not allowed here -- `vrmlalvh.s32 r0,sp,q2,q3'
|
||||
[^:]*:49: Error: r15 not allowed here -- `vrmlalvh.s32 r0,pc,q2,q3'
|
||||
[^:]*:50: Error: Odd register not allowed here -- `vrmlalvha.s32 r1,r1,q2,q3'
|
||||
[^:]*:51: Error: Even register not allowed here -- `vrmlalvha.s32 r0,r0,q2,q3'
|
||||
[^:]*:52: Error: r13 not allowed here -- `vrmlalvha.s32 r0,sp,q2,q3'
|
||||
[^:]*:53: Error: r15 not allowed here -- `vrmlalvha.s32 r0,pc,q2,q3'
|
||||
[^:]*:54: Error: Odd register not allowed here -- `vrmlsldavh.s32 r1,r1,q2,q3'
|
||||
[^:]*:55: Error: Even register not allowed here -- `vrmlsldavh.s32 r0,r0,q2,q3'
|
||||
[^:]*:56: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:57: Error: r15 not allowed here -- `vrmlsldavh.s32 r0,pc,q2,q3'
|
||||
[^:]*:58: Error: Odd register not allowed here -- `vrmlsldavha.s32 r1,r1,q2,q3'
|
||||
[^:]*:59: Error: Even register not allowed here -- `vrmlsldavha.s32 r0,r0,q2,q3'
|
||||
[^:]*:60: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:61: Error: r15 not allowed here -- `vrmlsldavha.s32 r0,pc,q2,q3'
|
||||
[^:]*:62: Error: Odd register not allowed here -- `vrmlsldavhx.s32 r1,r1,q2,q3'
|
||||
[^:]*:63: Error: Even register not allowed here -- `vrmlsldavhx.s32 r0,r0,q2,q3'
|
||||
[^:]*:64: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:65: Error: r15 not allowed here -- `vrmlsldavhx.s32 r0,pc,q2,q3'
|
||||
[^:]*:66: Error: Odd register not allowed here -- `vrmlsldavhax.s32 r1,r1,q2,q3'
|
||||
[^:]*:67: Error: Even register not allowed here -- `vrmlsldavhax.s32 r0,r0,q2,q3'
|
||||
[^:]*:68: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:69: Error: r15 not allowed here -- `vrmlsldavhax.s32 r0,pc,q2,q3'
|
||||
[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:81: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3'
|
||||
[^:]*:82: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3'
|
||||
[^:]*:84: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3'
|
||||
[^:]*:85: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavht.s32 r0,r1,q2,q3'
|
||||
[^:]*:87: Error: instruction missing MVE vector predication code -- `vrmlaldavh.s32 r0,r1,q2,q3'
|
||||
[^:]*:89: Error: syntax error -- `vrmlaldavhaeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:90: Error: syntax error -- `vrmlaldavhaeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:92: Error: syntax error -- `vrmlaldavhaeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:93: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavhat.s32 r0,r1,q2,q3'
|
||||
[^:]*:95: Error: instruction missing MVE vector predication code -- `vrmlaldavha.s32 r0,r1,q2,q3'
|
||||
[^:]*:97: Error: syntax error -- `vrmlaldavhxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:98: Error: syntax error -- `vrmlaldavhxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:100: Error: syntax error -- `vrmlaldavhxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:101: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavhxt.s32 r0,r1,q2,q3'
|
||||
[^:]*:103: Error: instruction missing MVE vector predication code -- `vrmlaldavhx.s32 r0,r1,q2,q3'
|
||||
[^:]*:105: Error: syntax error -- `vrmlaldavhaxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:106: Error: syntax error -- `vrmlaldavhaxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:108: Error: syntax error -- `vrmlaldavhaxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:109: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavhaxt.s32 r0,r1,q2,q3'
|
||||
[^:]*:111: Error: instruction missing MVE vector predication code -- `vrmlaldavhax.s32 r0,r1,q2,q3'
|
||||
[^:]*:113: Error: syntax error -- `vrmlalvheq.s32 r0,r1,q2,q3'
|
||||
[^:]*:114: Error: syntax error -- `vrmlalvheq.s32 r0,r1,q2,q3'
|
||||
[^:]*:116: Error: syntax error -- `vrmlalvheq.s32 r0,r1,q2,q3'
|
||||
[^:]*:117: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlalvht.s32 r0,r1,q2,q3'
|
||||
[^:]*:119: Error: instruction missing MVE vector predication code -- `vrmlalvh.s32 r0,r1,q2,q3'
|
||||
[^:]*:121: Error: syntax error -- `vrmlalvhaeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:122: Error: syntax error -- `vrmlalvhaeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:124: Error: syntax error -- `vrmlalvhaeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:125: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlalvhat.s32 r0,r1,q2,q3'
|
||||
[^:]*:127: Error: instruction missing MVE vector predication code -- `vrmlalvha.s32 r0,r1,q2,q3'
|
||||
[^:]*:129: Error: syntax error -- `vrmlsldavheq.s32 r0,r1,q2,q3'
|
||||
[^:]*:130: Error: syntax error -- `vrmlsldavheq.s32 r0,r1,q2,q3'
|
||||
[^:]*:132: Error: syntax error -- `vrmlsldavheq.s32 r0,r1,q2,q3'
|
||||
[^:]*:133: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavht.s32 r0,r1,q2,q3'
|
||||
[^:]*:135: Error: instruction missing MVE vector predication code -- `vrmlsldavh.s32 r0,r1,q2,q3'
|
||||
[^:]*:137: Error: syntax error -- `vrmlsldavhaeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:138: Error: syntax error -- `vrmlsldavhaeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:140: Error: syntax error -- `vrmlsldavhaeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:141: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavhat.s32 r0,r1,q2,q3'
|
||||
[^:]*:143: Error: instruction missing MVE vector predication code -- `vrmlsldavha.s32 r0,r1,q2,q3'
|
||||
[^:]*:145: Error: syntax error -- `vrmlsldavhxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:146: Error: syntax error -- `vrmlsldavhxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:148: Error: syntax error -- `vrmlsldavhxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:149: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavhxt.s32 r0,r1,q2,q3'
|
||||
[^:]*:151: Error: instruction missing MVE vector predication code -- `vrmlsldavhx.s32 r0,r1,q2,q3'
|
||||
[^:]*:153: Error: syntax error -- `vrmlsldavhaxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:154: Error: syntax error -- `vrmlsldavhaxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:156: Error: syntax error -- `vrmlsldavhaxeq.s32 r0,r1,q2,q3'
|
||||
[^:]*:157: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavhaxt.s32 r0,r1,q2,q3'
|
||||
[^:]*:159: Error: instruction missing MVE vector predication code -- `vrmlsldavhax.s32 r0,r1,q2,q3'
|
||||
159
gas/testsuite/gas/arm/mve-vrmlaldavh-bad.s
Normal file
159
gas/testsuite/gas/arm/mve-vrmlaldavh-bad.s
Normal file
@ -0,0 +1,159 @@
|
||||
.macro cond op
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().s32 r0, r1, q2, q3
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vrmlaldavh.s16 r0, r1, q2, q3
|
||||
vrmlaldavh.i32 r0, r1, q2, q3
|
||||
vrmlaldavha.s16 r0, r1, q2, q3
|
||||
vrmlaldavha.i32 r0, r1, q2, q3
|
||||
vrmlalvh.s16 r0, r1, q2, q3
|
||||
vrmlalvh.i32 r0, r1, q2, q3
|
||||
vrmlalvha.s16 r0, r1, q2, q3
|
||||
vrmlalvha.i32 r0, r1, q2, q3
|
||||
vrmlaldavhx.u32 r0, r1, q2, q3
|
||||
vrmlaldavhax.u32 r0, r1, q2, q3
|
||||
vrmlaldavhx.i32 r0, r1, q2, q3
|
||||
vrmlaldavhax.i32 r0, r1, q2, q3
|
||||
vrmlsldavh.s16 r0, r1, q2, q3
|
||||
vrmlsldavh.u32 r0, r1, q2, q3
|
||||
vrmlsldavha.s16 r0, r1, q2, q3
|
||||
vrmlsldavha.u32 r0, r1, q2, q3
|
||||
vrmlsldavhx.s16 r0, r1, q2, q3
|
||||
vrmlsldavhx.u32 r0, r1, q2, q3
|
||||
vrmlsldavhax.s16 r0, r1, q2, q3
|
||||
vrmlsldavhax.u32 r0, r1, q2, q3
|
||||
vrmlaldavh.s32 r1, r1, q2, q3
|
||||
vrmlaldavh.s32 r0, r0, q2, q3
|
||||
vrmlaldavh.s32 r0, sp, q2, q3
|
||||
vrmlaldavh.s32 r0, pc, q2, q3
|
||||
vrmlaldavha.s32 r1, r1, q2, q3
|
||||
vrmlaldavha.s32 r0, r0, q2, q3
|
||||
vrmlaldavha.s32 r0, sp, q2, q3
|
||||
vrmlaldavha.s32 r0, pc, q2, q3
|
||||
vrmlaldavhx.s32 r1, r1, q2, q3
|
||||
vrmlaldavhx.s32 r0, r0, q2, q3
|
||||
vrmlaldavhx.s32 r0, sp, q2, q3
|
||||
vrmlaldavhx.s32 r0, pc, q2, q3
|
||||
vrmlaldavhax.s32 r1, r1, q2, q3
|
||||
vrmlaldavhax.s32 r0, r0, q2, q3
|
||||
vrmlaldavhax.s32 r0, sp, q2, q3
|
||||
vrmlaldavhax.s32 r0, pc, q2, q3
|
||||
vrmlalvh.s32 r1, r1, q2, q3
|
||||
vrmlalvh.s32 r0, r0, q2, q3
|
||||
vrmlalvh.s32 r0, sp, q2, q3
|
||||
vrmlalvh.s32 r0, pc, q2, q3
|
||||
vrmlalvha.s32 r1, r1, q2, q3
|
||||
vrmlalvha.s32 r0, r0, q2, q3
|
||||
vrmlalvha.s32 r0, sp, q2, q3
|
||||
vrmlalvha.s32 r0, pc, q2, q3
|
||||
vrmlsldavh.s32 r1, r1, q2, q3
|
||||
vrmlsldavh.s32 r0, r0, q2, q3
|
||||
vrmlsldavh.s32 r0, sp, q2, q3
|
||||
vrmlsldavh.s32 r0, pc, q2, q3
|
||||
vrmlsldavha.s32 r1, r1, q2, q3
|
||||
vrmlsldavha.s32 r0, r0, q2, q3
|
||||
vrmlsldavha.s32 r0, sp, q2, q3
|
||||
vrmlsldavha.s32 r0, pc, q2, q3
|
||||
vrmlsldavhx.s32 r1, r1, q2, q3
|
||||
vrmlsldavhx.s32 r0, r0, q2, q3
|
||||
vrmlsldavhx.s32 r0, sp, q2, q3
|
||||
vrmlsldavhx.s32 r0, pc, q2, q3
|
||||
vrmlsldavhax.s32 r1, r1, q2, q3
|
||||
vrmlsldavhax.s32 r0, r0, q2, q3
|
||||
vrmlsldavhax.s32 r0, sp, q2, q3
|
||||
vrmlsldavhax.s32 r0, pc, q2, q3
|
||||
cond vrmlaldavh
|
||||
cond vrmlaldavha
|
||||
cond vrmlaldavhx
|
||||
cond vrmlaldavhax
|
||||
cond vrmlalvh
|
||||
cond vrmlalvha
|
||||
cond vrmlsldavh
|
||||
cond vrmlsldavha
|
||||
cond vrmlsldavhx
|
||||
cond vrmlsldavhax
|
||||
it eq
|
||||
vrmlaldavheq.s32 r0, r1, q2, q3
|
||||
vrmlaldavheq.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlaldavheq.s32 r0, r1, q2, q3
|
||||
vrmlaldavht.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlaldavh.s32 r0, r1, q2, q3
|
||||
it eq
|
||||
vrmlaldavhaeq.s32 r0, r1, q2, q3
|
||||
vrmlaldavhaeq.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlaldavhaeq.s32 r0, r1, q2, q3
|
||||
vrmlaldavhat.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlaldavha.s32 r0, r1, q2, q3
|
||||
it eq
|
||||
vrmlaldavhxeq.s32 r0, r1, q2, q3
|
||||
vrmlaldavhxeq.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlaldavhxeq.s32 r0, r1, q2, q3
|
||||
vrmlaldavhxt.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlaldavhx.s32 r0, r1, q2, q3
|
||||
it eq
|
||||
vrmlaldavhaxeq.s32 r0, r1, q2, q3
|
||||
vrmlaldavhaxeq.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlaldavhaxeq.s32 r0, r1, q2, q3
|
||||
vrmlaldavhaxt.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlaldavhax.s32 r0, r1, q2, q3
|
||||
it eq
|
||||
vrmlalvheq.s32 r0, r1, q2, q3
|
||||
vrmlalvheq.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlalvheq.s32 r0, r1, q2, q3
|
||||
vrmlalvht.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlalvh.s32 r0, r1, q2, q3
|
||||
it eq
|
||||
vrmlalvhaeq.s32 r0, r1, q2, q3
|
||||
vrmlalvhaeq.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlalvhaeq.s32 r0, r1, q2, q3
|
||||
vrmlalvhat.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlalvha.s32 r0, r1, q2, q3
|
||||
it eq
|
||||
vrmlsldavheq.s32 r0, r1, q2, q3
|
||||
vrmlsldavheq.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlsldavheq.s32 r0, r1, q2, q3
|
||||
vrmlsldavht.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlsldavh.s32 r0, r1, q2, q3
|
||||
it eq
|
||||
vrmlsldavhaeq.s32 r0, r1, q2, q3
|
||||
vrmlsldavhaeq.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlsldavhaeq.s32 r0, r1, q2, q3
|
||||
vrmlsldavhat.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlsldavha.s32 r0, r1, q2, q3
|
||||
it eq
|
||||
vrmlsldavhxeq.s32 r0, r1, q2, q3
|
||||
vrmlsldavhxeq.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlsldavhxeq.s32 r0, r1, q2, q3
|
||||
vrmlsldavhxt.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlsldavhx.s32 r0, r1, q2, q3
|
||||
it eq
|
||||
vrmlsldavhaxeq.s32 r0, r1, q2, q3
|
||||
vrmlsldavhaxeq.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlsldavhaxeq.s32 r0, r1, q2, q3
|
||||
vrmlsldavhaxt.s32 r0, r1, q2, q3
|
||||
vpst
|
||||
vrmlsldavhax.s32 r0, r1, q2, q3
|
||||
Reference in New Issue
Block a user