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* mips-opc.c (mtpc, mfpc, mtps, mfps): Add r5900 variants.

Browse Source 
Also move 'P' handling out of vr5400 sanitized code so it can be used
on r5900 too.
This commit is contained in:
Jeff Law
1997-12-15 19:43:04 +00:00
parent bfdbb113ec
commit 91866cc9be
2 changed files with 214 additions and 191 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
start-sanitize-r5900
Mon Dec 15 12:43:36 1997 Jeffrey A Law (law@cygnus.com)
* mips-opc.c (mtpc, mfpc, mtps, mfps): Add r5900 variants.
end-sanitize-r5900
start-sanitize-tic80
Fri Dec 12 11:57:04 1997 Fred Fish <fnf@cygnus.com>

400
opcodes/mips-opc.c
View File

@ -125,7 +125,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO },
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */
@ -133,19 +133,19 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */
{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO },
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 },
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 },
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 },
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 },
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1},
{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1},
{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO },
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 },
{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO },
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 },
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
/* b is at the top of the table. */
/* bal is at the top of the table. */
@ -172,49 +172,49 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 },
{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO },
{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 },
{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
{"beql", "s,I,p", 2, (int) M_BEQL_I, INSN_MACRO },
{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO },
{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO },
{"bgel", "s,t,p", 2, (int) M_BGEL, INSN_MACRO },
{"bgel", "s,I,p", 2, (int) M_BGEL_I, INSN_MACRO },
{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO },
{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO },
{"bgeul", "s,t,p", 2, (int) M_BGEUL, INSN_MACRO },
{"bgeul", "s,I,p", 2, (int) M_BGEUL_I, INSN_MACRO },
{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2 },
{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 },
{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 },
{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2 },
{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2 },
{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 },
{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 },
{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2 },
{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2 },
{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 },
{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 },
{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 },
{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO },
{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO },
{"bgtl", "s,t,p", 2, (int) M_BGTL, INSN_MACRO },
{"bgtl", "s,I,p", 2, (int) M_BGTL_I, INSN_MACRO },
{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO },
{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO },
{"bgtul", "s,t,p", 2, (int) M_BGTUL, INSN_MACRO },
{"bgtul", "s,I,p", 2, (int) M_BGTUL_I, INSN_MACRO },
{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 },
{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 },
{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2 },
{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2 },
{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 },
{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 },
{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2 },
{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2 },
{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 },
{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO },
{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO },
{"blel", "s,t,p", 2, (int) M_BLEL, INSN_MACRO },
{"blel", "s,I,p", 2, (int) M_BLEL_I, INSN_MACRO },
{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO },
{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO },
{"bleul", "s,t,p", 2, (int) M_BLEUL, INSN_MACRO },
{"bleul", "s,I,p", 2, (int) M_BLEUL_I, INSN_MACRO },
{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 },
{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 },
{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2 },
{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2 },
{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 },
{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 },
{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2 },
{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2 },
{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 },
{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO },
{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO },
{"bltl", "s,t,p", 2, (int) M_BLTL, INSN_MACRO },
{"bltl", "s,I,p", 2, (int) M_BLTL_I, INSN_MACRO },
{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO },
{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO },
{"bltul", "s,t,p", 2, (int) M_BLTUL, INSN_MACRO },
{"bltul", "s,I,p", 2, (int) M_BLTUL_I, INSN_MACRO },
{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 },
{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 },
{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2 },
{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2 },
{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 },
{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 },
{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2 },
{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2 },
{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 },
{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 },
{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
@ -222,9 +222,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 },
{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO },
{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 },
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
{"bnel", "s,I,p", 2, (int) M_BNEL_I, INSN_MACRO },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 },
{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
{"break", "c", 0x0000000d, 0xfc00003f, TRAP, I1 },
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
@ -316,13 +316,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 },
{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 },
{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 },
{"dabs", "d,v", 3, (int) M_DABS, INSN_MACRO },
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 },
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
{"dadd", "t,r,I", 3, (int) M_DADD_I, INSN_MACRO },
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 },
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 },
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 },
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
{"daddu", "t,r,I", 3, (int) M_DADDU_I, INSN_MACRO },
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 },
/* start-sanitize-vr5400 */
{"dbreak", "", 0x7000003f, 0xffffffff, 0, N5 },
/* end-sanitize-vr5400 */
@ -332,20 +332,20 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"deret", "", 0x4200001f, 0xffffffff, 0, G2 },
/* For ddiv, see the comments about div. */
{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
{"ddiv", "d,v,t", 3, (int) M_DDIV_3, INSN_MACRO },
{"ddiv", "d,v,I", 3, (int) M_DDIV_3I, INSN_MACRO },
{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 },
{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 },
/* For ddivu, see the comments about div. */
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
{"ddivu", "d,v,t", 3, (int) M_DDIVU_3, INSN_MACRO },
{"ddivu", "d,v,I", 3, (int) M_DDIVU_3I, INSN_MACRO },
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 },
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 },
/* The MIPS assembler treats the div opcode with two operands as
though the first operand appeared twice (the first operand is both
a source and a destination). To get the div machine instruction,
you must use an explicit destination of $0. */
{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO },
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO },
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 },
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 },
/* start-sanitize-r5900 */
{"div1", "s,t", 0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
/* end-sanitize-r5900 */
@ -354,26 +354,26 @@ const struct mips_opcode mips_builtin_opcodes[] = {
/* For divu, see the comments about div. */
{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO },
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO },
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 },
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 },
/* start-sanitize-r5900 */
{"divu1", "s,t", 0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
/* end-sanitize-r5900 */
{"dla", "t,A(b)", 3, (int) M_DLA_AB, INSN_MACRO },
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 },
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */
{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */
{"dli", "t,I", 3, (int) M_DLI, INSN_MACRO },
{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 },
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO, V1 },
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 },
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
{"dmul", "d,v,t", 3, (int) M_DMUL, INSN_MACRO },
{"dmul", "d,v,I", 3, (int) M_DMUL_I, INSN_MACRO },
{"dmulo", "d,v,t", 3, (int) M_DMULO, INSN_MACRO },
{"dmulo", "d,v,I", 3, (int) M_DMULO_I, INSN_MACRO },
{"dmulou", "d,v,t", 3, (int) M_DMULOU, INSN_MACRO },
{"dmulou", "d,v,I", 3, (int) M_DMULOU_I, INSN_MACRO },
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 },
{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 },
{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 },
{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 },
{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 },
{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 },
{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3},
/* start-sanitize-tx49 */
{"dmult", "d,s,t", 0x0000001c, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T4},
@ -385,11 +385,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO },
{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO },
{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 },
{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 },
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
/* start-sanitize-vr5400 */
{"dret", "", 0x7000003e, 0xffffffff, 0, N5 },
{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, N5 },
@ -413,9 +413,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */
{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 },
{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
{"dsub", "d,v,I", 3, (int) M_DSUB_I, INSN_MACRO },
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
{"dsubu", "d,v,I", 3, (int) M_DSUBU_I, INSN_MACRO },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
{"eret", "", 0x42000018, 0xffffffff, 0, I3 },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
@ -429,7 +429,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */
/* SVR4 PIC code requires special handling for j, so it must be a
macro. */
{"j", "a", 0, (int) M_J_A, INSN_MACRO },
{"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 },
/* This form of j is used by the disassembler and internally by the
assembler, but will never match user input (because the line above
will match first). */
@ -438,9 +438,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 },
/* SVR4 PIC code requires special handling for jal, so it must be a
macro. */
{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO },
{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO },
{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO },
{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 },
{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 },
{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 },
/* This form of jal is used by the disassembler and internally by the
assembler, but will never match user input (because the line above
will match first). */
@ -448,71 +448,71 @@ const struct mips_opcode mips_builtin_opcodes[] = {
/* jalx really should only be avaliable if mips16 is available,
but for now make it I1. */
{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 },
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO },
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 },
{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO },
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 },
{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO },
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 },
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO },
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 },
{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
{"ldc1", "T,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
{"ldc1", "E,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO },
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO },
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 },
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 },
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
{"ldc2", "E,A(b)", 2, (int) M_LDC2_AB, INSN_MACRO },
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 },
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
{"ldc3", "E,A(b)", 2, (int) M_LDC3_AB, INSN_MACRO },
{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 },
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
{"ldl", "t,A(b)", 3, (int) M_LDL_AB, INSN_MACRO },
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 },
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
{"ldr", "t,A(b)", 3, (int) M_LDR_AB, INSN_MACRO },
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 },
{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO },
{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 },
{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO },
{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 },
/* li is at the start of the table. */
{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO },
{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO },
{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO },
{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO },
{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 },
{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 },
{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 },
{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 },
{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 },
{"ll", "t,A(b)", 2, (int) M_LL_AB, INSN_MACRO },
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 },
{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
{"lld", "t,A(b)", 3, (int) M_LLD_AB, INSN_MACRO },
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 },
{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 },
/* start-sanitize-r5900 */
{"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_t|RD_b, T5 },
/* end-sanitize-r5900 */
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO },
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 },
{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO },
{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 },
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO },
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 },
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO },
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 },
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO },
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 },
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
{"lcache", "t,A(b)", 2, (int) M_LWL_AB, INSN_MACRO }, /* as lwl */
{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */
{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO },
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 },
{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
{"flush", "t,A(b)", 2, (int) M_LWR_AB, INSN_MACRO }, /* as lwr */
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */
{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
{"lwu", "t,A(b)", 3, (int) M_LWU_AB, INSN_MACRO },
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 },
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
/* start-sanitize-vr5400 */
{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d, N5 },
@ -545,10 +545,28 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 },
/* start-sanitize-vr5400 */
{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, RD_C0|WR_t, N5 },
/* end-sanitize-vr5400 */
/* start-sanitize-r5900 */
{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, RD_C0|WR_t, T5 },
/* end-sanitize-r5900 */
/* start-sanitize-vr5400 */
{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, RD_C0|WR_t, N5 },
/* end-sanitize-vr5400 */
/* start-sanitize-r5900 */
{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, RD_C0|WR_t, T5 },
/* end-sanitize-r5900 */
/* start-sanitize-vr5400 */
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, WR_C0|RD_t, N5 },
/* end-sanitize-vr5400 */
/* start-sanitize-r5900 */
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, WR_C0|RD_t, T5 },
/* end-sanitize-r5900 */
/* start-sanitize-vr5400 */
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, WR_C0|RD_t, N5 },
/* end-sanitize-vr5400 */
/* start-sanitize-r5900 */
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, WR_C0|RD_t, T5 },
/* end-sanitize-r5900 */
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
@ -630,12 +648,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
/* end-sanitize-vr5400 */
{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, P3 },
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO },
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO },
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO },
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO },
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO },
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
/* start-sanitize-vr5400 */
{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
@ -662,10 +680,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
/* nop is at the start of the table. */
{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO },
{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 },
{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO },
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 },
{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
/* start-sanitize-r5900 */
@ -802,19 +820,19 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO },
{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO },
{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 },
{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 },
{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO },
{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO },
{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 },
{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 },
{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO },
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO },
{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 },
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 },
/* start-sanitize-vr5400 */
{"ror", "d,t,<", 0x00200002, 0xffe0003f, WR_d|RD_t, N5 },
/* end-sanitize-vr5400 */
{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO },
{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO },
{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 },
{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 },
/* start-sanitize-vr5400 */
{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, N5 },
/* end-sanitize-vr5400 */
@ -828,61 +846,61 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, T5 },
/* end-sanitize-r5900 */
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO },
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 },
{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 },
{"sc", "t,A(b)", 2, (int) M_SC_AB, INSN_MACRO },
{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 },
{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 },
{"scd", "t,A(b)", 3, (int) M_SCD_AB, INSN_MACRO },
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 },
{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO },
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 },
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 },
{"sdbbp", "c", 0x0000000e, 0xfc00003f, TRAP, G2 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "T,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
{"sdc1", "E,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 },
{"sdc2", "E,A(b)", 2, (int) M_SDC2_AB, INSN_MACRO },
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 },
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 },
{"sdc3", "E,A(b)", 2, (int) M_SDC3_AB, INSN_MACRO },
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 },
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b, I2 },
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO },
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 },
{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 },
{"sdl", "t,A(b)", 3, (int) M_SDL_AB, INSN_MACRO },
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 },
{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 },
{"sdr", "t,A(b)", 3, (int) M_SDR_AB, INSN_MACRO },
{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 },
{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,L1 },
{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,L1 },
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO },
{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO },
{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO },
{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO },
{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO },
{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO },
{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO },
{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO },
{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO },
{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO },
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 },
{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 },
{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 },
{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 },
{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 },
{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 },
{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 },
{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 },
{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 },
{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 },
{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 },
{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO },
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO },
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO },
{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO },
{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO },
{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 },
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 },
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 },
{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 },
{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 },
{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */
{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 },
{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO },
{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 },
{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 },
{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 },
{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO },
{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO },
{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO },
{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 },
{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 },
{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 },
/* start-sanitize-r5900 */
{"sq", "t,o(b)", 0x7c000000, 0xfc000000, SM|RD_t|RD_b, T5 },
/* end-sanitize-r5900 */
@ -896,34 +914,34 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
{"standby", "", 0x42000021, 0xffffffff, 0, V1 },
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO },
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO },
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 },
{"suspend", "", 0x42000022, 0xffffffff, 0, V1 },
{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 },
{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO },
{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 },
{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 },
{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO },
{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 },
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 },
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO },
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 },
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 },
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO },
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 },
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO },
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 },
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
{"scache", "t,A(b)", 2, (int) M_SWL_AB, INSN_MACRO }, /* as swl */
{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */
{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO },
{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 },
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
{"invalidate", "t,A(b)",2, (int) M_SWR_AB, INSN_MACRO }, /* as swr */
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */
{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
{"sync", "", 0x0000000f, 0xffffffff, 0, I2|T3 },
{"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 },
@ -931,15 +949,15 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 },
{"teq", "s,t", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */
{"teq", "s,I", 2, (int) M_TEQ_I, INSN_MACRO },
{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 },
{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 },
{"tge", "s,t", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */
{"tge", "s,I", 2, (int) M_TGE_I, INSN_MACRO },
{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 },
{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 },
{"tgeu", "s,t", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
{"tgeu", "s,I", 2, (int) M_TGEU_I, INSN_MACRO },
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 },
{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 },
{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 },
{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 },
@ -947,39 +965,39 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
{"tlt", "s,t", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */
{"tlt", "s,I", 2, (int) M_TLT_I, INSN_MACRO },
{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 },
{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 },
{"tltu", "s,t", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */
{"tltu", "s,I", 2, (int) M_TLTU_I, INSN_MACRO },
{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 },
{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 },
{"tne", "s,t", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */
{"tne", "s,I", 2, (int) M_TNE_I, INSN_MACRO },
{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 },
{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 },
{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO },
{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 },
{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO },
{"uld", "t,o(b)", 3, (int) M_ULD, INSN_MACRO },
{"uld", "t,A(b)", 3, (int) M_ULD_A, INSN_MACRO },
{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO },
{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO },
{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO },
{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO },
{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO },
{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO },
{"usd", "t,o(b)", 3, (int) M_USD, INSN_MACRO },
{"usd", "t,A(b)", 3, (int) M_USD_A, INSN_MACRO },
{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO },
{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO },
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO },
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO },
{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 },
{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 },
{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 },
{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 },
{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 },
{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 },
{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 },
{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 },
{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 },
{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 },
{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 },
{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 },
{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 },
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 },
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 },
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
{"wait", "", 0x42000020, 0xffffffff, TRAP, I3 },
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
@ -1063,10 +1081,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },
{"c3", "C", 0x4e000000, 0xfe000000, 0, I1 },
{"cop0", "C", 0, (int) M_COP0, INSN_MACRO },
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO },
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO },
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO },
{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 },
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 },
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 },
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 },
};
#define MIPS_NUM_OPCODES \