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sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set

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The Blackfin PRM says that the top 8 bits of the accumulator must be
cleared when using the VIT_MAX insn, so the sim has followed this spec.
Matching the hardware behavior though when the high bits are not cleared
is easy to do and doesn't break existing behavior, so go for it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
2011-03-24 03:14:20 +00:00
parent de0addfbef
commit 8e670c0a3f
2 changed files with 7 additions and 2 deletions
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5
sim/bfin/ChangeLog
View File

@ -1,3 +1,8 @@
2011-03-23 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32shift_0): Set acc0 to the unextended
value for the VIT_MAX insn, and mask off the result when done.
2011-03-23 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Set A1 to a1_lo when up_hi is false,

4
sim/bfin/bfin-sim.c
View File

@ -5425,7 +5425,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
}
else if ((sop == 0 || sop == 1) && sopcde == 9)
{
bs40 acc0 = get_extended_acc (cpu, 0);
bs40 acc0 = get_unextended_acc (cpu, 0);
bs16 sL, sH, out;
TRACE_INSN (cpu, "R%i.L = VIT_MAX (R%i) (AS%c);",
@ -5435,7 +5435,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
sH = DREG (src1) >> 16;
if (sop & 1)
acc0 >>= 1;
acc0 = (acc0 & 0xfeffffffffull) >> 1;
else
acc0 <<= 1;