espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-24 04:00:07 +08:00
Code Issues Packages Projects Releases Wiki Activity

[PATCH 20/57][Arm][GAS] Add support for MVE instructions: vmaxnmv, vmaxnmav, vminnmv and vminnmav

Browse Source 
gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (do_mve_vmaxnmv): New encoding function.
	(insns): Add entries for new mnemonics.
	* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d: New test.
	* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l: New test.
	* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s: New test.
This commit is contained in:
Andre Vieira
2019-05-16 11:42:52 +01:00
parent 935295b51d
commit 8cd7817067
5 changed files with 151 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
gas/ChangeLog
View File

@ -1,3 +1,11 @@
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmaxnmv): New encoding function.
(insns): Add entries for new mnemonics.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s: New test.
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmaxa_vmina): New encoding function.

24
gas/config/tc-arm.c
View File

@ -17248,6 +17248,26 @@ do_mve_vmladav (void)
inst.instruction |= (et.size == 32) << 16;
}
static void
do_mve_vmaxnmv (void)
{
enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
struct neon_type_el et
= neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
if (inst.cond > COND_ALWAYS)
inst.pred_insn_type = INSIDE_VPT_INSN;
else
inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
if (inst.operands[0].reg == REG_SP)
as_tsktsk (MVE_BAD_SP);
else if (inst.operands[0].reg == REG_PC)
as_tsktsk (MVE_BAD_PC);
mve_encode_rq (et.size == 16, 64);
}
static void
do_neon_qrdmlah (void)
{
@ -24421,6 +24441,10 @@ static const struct asm_opcode insns[] =
mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv),
mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv),
mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv),
mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_vfp_ext_v1

5
gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d Normal file
View File

@ -0,0 +1,5 @@
#name: bad MVE VMAXNMV, VMAXNMAV, VMINNMV and VMINNMAV instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vmaxnmv-vminnmv-bad.l
.*: +file format .*arm.*

57
gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l Normal file
View File

@ -0,0 +1,57 @@
[^:]*: Assembler messages:
[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnmv.f64 r0,q1'
[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnmv.i16 r0,q1'
[^:]*:12: Error: bad type in SIMD instruction -- `vminnmv.f64 r0,q1'
[^:]*:13: Error: bad type in SIMD instruction -- `vminnmv.i16 r0,q1'
[^:]*:14: Error: bad type in SIMD instruction -- `vmaxnmav.f64 r0,q1'
[^:]*:15: Error: bad type in SIMD instruction -- `vmaxnmav.i16 r0,q1'
[^:]*:16: Error: bad type in SIMD instruction -- `vminnmav.f64 r0,q1'
[^:]*:17: Error: bad type in SIMD instruction -- `vminnmav.i16 r0,q1'
[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Error: syntax error -- `vmaxnmveq.f32 r0,q1'
[^:]*:28: Error: syntax error -- `vmaxnmveq.f32 r0,q1'
[^:]*:30: Error: syntax error -- `vmaxnmveq.f32 r0,q1'
[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmvt.f32 r0,q1'
[^:]*:33: Error: instruction missing MVE vector predication code -- `vmaxnmv.f32 r0,q1'
[^:]*:35: Error: syntax error -- `vmaxnmaveq.f32 r0,q1'
[^:]*:36: Error: syntax error -- `vmaxnmaveq.f32 r0,q1'
[^:]*:38: Error: syntax error -- `vmaxnmaveq.f32 r0,q1'
[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmavt.f32 r0,q1'
[^:]*:41: Error: instruction missing MVE vector predication code -- `vmaxnmav.f32 r0,q1'
[^:]*:43: Error: syntax error -- `vminnmveq.f32 r0,q1'
[^:]*:44: Error: syntax error -- `vminnmveq.f32 r0,q1'
[^:]*:46: Error: syntax error -- `vminnmveq.f32 r0,q1'
[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmvt.f32 r0,q1'
[^:]*:49: Error: instruction missing MVE vector predication code -- `vminnmv.f32 r0,q1'
[^:]*:51: Error: syntax error -- `vminnmaveq.f32 r0,q1'
[^:]*:52: Error: syntax error -- `vminnmaveq.f32 r0,q1'
[^:]*:54: Error: syntax error -- `vminnmaveq.f32 r0,q1'
[^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmavt.f32 r0,q1'
[^:]*:57: Error: instruction missing MVE vector predication code -- `vminnmav.f32 r0,q1'

57
gas/testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s Normal file
View File

@ -0,0 +1,57 @@
.macro cond, op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().f16 r0, q1
.endr
.endm
.syntax unified
.thumb
vmaxnmv.f64 r0, q1
vmaxnmv.i16 r0, q1
vminnmv.f64 r0, q1
vminnmv.i16 r0, q1
vmaxnmav.f64 r0, q1
vmaxnmav.i16 r0, q1
vminnmav.f64 r0, q1
vminnmav.i16 r0, q1
vmaxnmv.f16 sp, q1
vmaxnmav.f32 pc, q1
vminnmav.f16 sp, q1
vminnmv.f32 pc, q1
cond vmaxnmv
cond vminnmv
cond vmaxnmav
cond vminnmav
it eq
vmaxnmveq.f32 r0, q1
vmaxnmveq.f32 r0, q1
vpst
vmaxnmveq.f32 r0, q1
vmaxnmvt.f32 r0, q1
vpst
vmaxnmv.f32 r0, q1
it eq
vmaxnmaveq.f32 r0, q1
vmaxnmaveq.f32 r0, q1
vpst
vmaxnmaveq.f32 r0, q1
vmaxnmavt.f32 r0, q1
vpst
vmaxnmav.f32 r0, q1
it eq
vminnmveq.f32 r0, q1
vminnmveq.f32 r0, q1
vpst
vminnmveq.f32 r0, q1
vminnmvt.f32 r0, q1
vpst
vminnmv.f32 r0, q1
it eq
vminnmaveq.f32 r0, q1
vminnmaveq.f32 r0, q1
vpst
vminnmaveq.f32 r0, q1
vminnmavt.f32 r0, q1
vpst
vminnmav.f32 r0, q1