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x86: Support VEX base opcode length > 1
Intel AMX instructions with 8-bit immediate opcode extension without operands: tilerelease, 0, 0x49c0, None, 2, CpuAMX_TILE|Cpu64, Vex|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } Update build_vex_prefix to support VEX base opcode length > 1. * tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1. (md_assemble): Don't process ImmExt without operands.
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@ -1,3 +1,8 @@
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2020-06-29 H.J. Lu <hongjiu.lu@intel.com>
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* tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
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(md_assemble): Don't process ImmExt without operands.
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2020-06-29 Hans-Peter Nilsson <hp@bitrange.com>
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2020-06-29 Hans-Peter Nilsson <hp@bitrange.com>
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PR gas/25331
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PR gas/25331
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@ -3664,7 +3664,7 @@ build_vex_prefix (const insn_template *t)
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}
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}
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}
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}
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switch ((i.tm.base_opcode >> 8) & 0xff)
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switch ((i.tm.base_opcode >> (i.tm.opcode_length << 3)) & 0xff)
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{
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{
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case 0:
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case 0:
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implied_prefix = 0;
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implied_prefix = 0;
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@ -4873,12 +4873,8 @@ md_assemble (char *line)
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if (!process_operands ())
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if (!process_operands ())
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return;
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return;
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}
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}
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else
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else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
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{
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{
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if (i.tm.opcode_modifier.immext)
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process_immext ();
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if (!quiet_warnings && i.tm.opcode_modifier.ugh)
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/* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
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/* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
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as_warn (_("translating to `%sp'"), i.tm.name);
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as_warn (_("translating to `%sp'"), i.tm.name);
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}
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}
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