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x86: Support VEX base opcode length > 1

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Intel AMX instructions with 8-bit immediate opcode extension without
operands:

tilerelease, 0, 0x49c0, None, 2, CpuAMX_TILE|Cpu64, Vex|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

Update build_vex_prefix to support VEX base opcode length > 1.

	* tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
	(md_assemble): Don't process ImmExt without operands.
This commit is contained in:
H.J. Lu
2020-06-29 06:28:31 -07:00
parent a57f74bb7c
commit 8c190ce038
2 changed files with 7 additions and 6 deletions
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5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2020-06-29 H.J. Lu <hongjiu.lu@intel.com>
* tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
(md_assemble): Don't process ImmExt without operands.
2020-06-29 Hans-Peter Nilsson <hp@bitrange.com>
PR gas/25331

8
gas/config/tc-i386.c
View File

@ -3664,7 +3664,7 @@ build_vex_prefix (const insn_template *t)
}
}
switch ((i.tm.base_opcode >> 8) & 0xff)
switch ((i.tm.base_opcode >> (i.tm.opcode_length << 3)) & 0xff)
{
case 0:
implied_prefix = 0;
@ -4873,12 +4873,8 @@ md_assemble (char *line)
if (!process_operands ())
return;
}
else
else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
{
if (i.tm.opcode_modifier.immext)
process_immext ();
if (!quiet_warnings && i.tm.opcode_modifier.ugh)
/* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
as_warn (_("translating to `%sp'"), i.tm.name);
}