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RISC-V: Linux signal frame support.

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Make riscv_isa_flen available to the linux native code, and clean up duplicate
comments.

	gdb/
	* riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
	(riscv_isa_flen): Likewise.  Drop static.
	* riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
	(riscv_isa_flen): Likewise.
This commit is contained in:
Jim Wilson
2018-10-26 10:29:46 -07:00
parent 8d619c01db
commit 8a61382623
3 changed files with 20 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
gdb/ChangeLog
View File

@ -1,3 +1,10 @@
2018-10-26 Jim Wilson <jimw@sifive.com>
* riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
(riscv_isa_flen): Likewise. Drop static.
* riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
(riscv_isa_flen): Likewise. Declare.
2018-10-26 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>

11
gdb/riscv-tdep.c
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@ -349,9 +349,7 @@ riscv_has_feature (struct gdbarch *gdbarch, char feature)
return (misa & (1 << (feature - 'A'))) != 0;
}
/* Return the width in bytes of the general purpose registers for GDBARCH.
Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
RV128. */
/* See riscv-tdep.h. */
int
riscv_isa_xlen (struct gdbarch *gdbarch)
@ -370,12 +368,9 @@ riscv_isa_xlen (struct gdbarch *gdbarch)
}
}
/* Return the width in bytes of the floating point registers for GDBARCH.
If this architecture has no floating point registers, then return 0.
Possible values are 4, 8, or 16 for depending on which of single, double
or quad floating point support is available. */
/* See riscv-tdep.h. */
static int
int
riscv_isa_flen (struct gdbarch *gdbarch)
{
if (riscv_has_feature (gdbarch, 'Q'))

11
gdb/riscv-tdep.h
View File

@ -84,9 +84,18 @@ struct gdbarch_tdep
struct type *riscv_fpreg_q_type;
};
/* Return the width in bytes of the general purpose registers for GDBARCH. */
/* Return the width in bytes of the general purpose registers for GDBARCH.
Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
RV128. */
extern int riscv_isa_xlen (struct gdbarch *gdbarch);
/* Return the width in bytes of the floating point registers for GDBARCH.
If this architecture has no floating point registers, then return 0.
Possible values are 4, 8, or 16 for depending on which of single, double
or quad floating point support is available. */
extern int riscv_isa_flen (struct gdbarch *gdbarch);
/* Single step based on where the current instruction will take us. */
extern std::vector<CORE_ADDR> riscv_software_single_step
(struct regcache *regcache);