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[PATCH 5/57][Arm][GAS] Add support for MVE instructions: vmull{b,t}
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (BAD_MVE_AUTO): New error message. (BAD_MVE_SRCDEST): Likewise. (mark_feature_used): Diagnose MVE only instructions when in auto-detection mode or -march=all. (enum operand_parse_code): Define new operand. (parse_operands): Handle new operand. (M_MNEM_vmullt, M_MNEM_vmullb): New encodings. (mve_encode_qqq): New encoding helper function. (do_mve_vmull): New encoding function. (insns): Handle new instructions. * testsuite/gas/arm/mve-vmullbt-bad.d: New test. * testsuite/gas/arm/mve-vmullbt-bad.l: New test. * testsuite/gas/arm/mve-vmullbt-bad.s: New test.
This commit is contained in:
Andre Vieira
@ -1,3 +1,19 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (BAD_MVE_AUTO): New error message.
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(BAD_MVE_SRCDEST): Likewise.
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(mark_feature_used): Diagnose MVE only instructions when in
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auto-detection mode or -march=all.
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(enum operand_parse_code): Define new operand.
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(parse_operands): Handle new operand.
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(M_MNEM_vmullt, M_MNEM_vmullb): New encodings.
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(mve_encode_qqq): New encoding helper function.
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(do_mve_vmull): New encoding function.
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(insns): Handle new instructions.
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* testsuite/gas/arm/mve-vmullbt-bad.d: New test.
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* testsuite/gas/arm/mve-vmullbt-bad.l: New test.
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* testsuite/gas/arm/mve-vmullbt-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (struct asm_opcode): Make avalue a full int.
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@ -887,6 +887,11 @@ struct asm_opcode
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#define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
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" operand")
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#define BAD_SIMD_TYPE _("bad type in SIMD instruction")
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#define BAD_MVE_AUTO \
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_("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
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" use a valid -march or -mcpu option.")
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#define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
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"and source operands makes instruction UNPREDICTABLE")
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static struct hash_control * arm_ops_hsh;
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static struct hash_control * arm_cond_hsh;
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@ -1538,6 +1543,15 @@ record_feature_use (const arm_feature_set *feature)
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static bfd_boolean
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mark_feature_used (const arm_feature_set *feature)
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{
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/* Do not support the use of MVE only instructions when in auto-detection or
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-march=all. */
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if (((feature == &mve_ext) || (feature == &mve_fp_ext))
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&& ARM_CPU_IS_ANY (cpu_variant))
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{
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first_error (BAD_MVE_AUTO);
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return FALSE;
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}
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/* Ensure the option is valid on the current architecture. */
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
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return FALSE;
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@ -6740,6 +6754,8 @@ enum operand_parse_code
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OP_RR_RNSC, /* ARM reg or Neon scalar. */
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OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
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OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
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OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
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*/
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OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
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OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
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OP_VMOV, /* Neon VMOV operands. */
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@ -7091,6 +7107,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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}
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break;
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case OP_RNSDQ_RNSC_MQ:
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po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc);
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break;
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try_rnsdq_rnsc:
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case OP_RNSDQ_RNSC:
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{
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po_scalar_or_goto (8, try_nsdq);
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@ -13833,6 +13853,8 @@ do_t_loloop (void)
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#define M_MNEM_vmlsdava 0xeef00e21
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#define M_MNEM_vmlsdavx 0xeef01e01
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#define M_MNEM_vmlsdavax 0xeef01e21
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#define M_MNEM_vmullt 0xee011e00
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#define M_MNEM_vmullb 0xee010e00
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/* Neon instruction encoder helpers. */
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@ -15220,6 +15242,23 @@ mve_encode_rqq (unsigned bit28, unsigned size)
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inst.is_neon = 1;
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}
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static void
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mve_encode_qqq (int ubit, int size)
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{
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inst.instruction |= (ubit != 0) << 28;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= neon_logbits (size) << 20;
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inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[1].reg) << 7;
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inst.instruction |= HI1 (inst.operands[2].reg) << 5;
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inst.instruction |= LOW4 (inst.operands[2].reg);
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inst.is_neon = 1;
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}
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/* Encode insns with bit pattern:
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|28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
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@ -15938,6 +15977,61 @@ do_neon_qdmulh (void)
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}
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}
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static void
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do_mve_vmull (void)
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{
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enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
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NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
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&& inst.cond == COND_ALWAYS
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&& ((unsigned)inst.instruction) == M_MNEM_vmullt)
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{
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if (rs == NS_QQQ)
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{
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struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
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N_SUF_32 | N_F64 | N_P8
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| N_P16 | N_I_MVE | N_KEY);
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if (((et.type == NT_poly) && et.size == 8
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&& ARM_CPU_IS_ANY (cpu_variant))
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|| (et.type == NT_integer) || (et.type == NT_float))
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goto neon_vmul;
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}
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else
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goto neon_vmul;
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}
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constraint (rs != NS_QQQ, BAD_FPU);
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struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
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N_SU_32 | N_P8 | N_P16 | N_KEY);
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/* We are dealing with MVE's vmullt. */
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if (et.size == 32
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&& (inst.operands[0].reg == inst.operands[1].reg
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|| inst.operands[0].reg == inst.operands[2].reg))
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as_tsktsk (BAD_MVE_SRCDEST);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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if (et.type == NT_poly)
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mve_encode_qqq (neon_logbits (et.size), 64);
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else
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mve_encode_qqq (et.type == NT_unsigned, et.size);
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return;
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neon_vmul:
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inst.instruction = N_MNEM_vmul;
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inst.cond = 0xb;
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if (thumb_mode)
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inst.pred_insn_type = INSIDE_IT_INSN;
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do_neon_mul ();
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}
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static void
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do_mve_vabav (void)
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{
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@ -22748,6 +22842,7 @@ static const struct asm_opcode insns[] =
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ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
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/* MVE and MVE FP only. */
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mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull),
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mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
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mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
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mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
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@ -22765,8 +22860,9 @@ static const struct asm_opcode insns[] =
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v6t2
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mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
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mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
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mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull),
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mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
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mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
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MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
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MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
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5
gas/testsuite/gas/arm/mve-vmullbt-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vmullbt-bad.d
Normal file
@ -0,0 +1,5 @@
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#name: bad MVE VMULL instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vmullbt-bad.l
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.*: +file format .*arm.*
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33
gas/testsuite/gas/arm/mve-vmullbt-bad.l
Normal file
33
gas/testsuite/gas/arm/mve-vmullbt-bad.l
Normal file
@ -0,0 +1,33 @@
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[^:]*: Assembler messages:
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[^:]*:13: Error: bad type in SIMD instruction -- `vmullb.s64 q0,q1,q2'
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[^:]*:14: Error: bad type in SIMD instruction -- `vmullb.f16 q0,q1,q2'
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[^:]*:15: Error: bad type in SIMD instruction -- `vmullb.f32 q0,q1,q2'
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[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Error: bad type in SIMD instruction -- `vmullt.s64 q0,q1,q2'
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[^:]*:20: Error: bad type in SIMD instruction -- `vmullt.f16 q0,q1,q2'
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[^:]*:21: Error: bad type in SIMD instruction -- `vmullt.f32 q0,q1,q2'
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[^:]*:22: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:23: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Error: syntax error -- `vmullbeq.s32 q0,q1,q2'
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[^:]*:27: Error: syntax error -- `vmullbeq.s32 q0,q1,q2'
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[^:]*:29: Error: syntax error -- `vmullbeq.s32 q0,q1,q2'
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[^:]*:31: Error: instruction missing MVE vector predication code -- `vmullb.s32 q0,q1,q2'
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[^:]*:32: Error: vector predicated instruction should be in VPT/VPST block -- `vmullbt.s32 q0,q1,q2'
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[^:]*:34: Error: syntax error -- `vmullteq.s32 q0,q1,q2'
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[^:]*:35: Error: syntax error -- `vmullteq.s32 q0,q1,q2'
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[^:]*:37: Error: syntax error -- `vmullteq.s32 q0,q1,q2'
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[^:]*:39: Error: instruction missing MVE vector predication code -- `vmullt.s32 q0,q1,q2'
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[^:]*:40: Error: vector predicated instruction should be in VPT/VPST block -- `vmulltt.s32 q0,q1,q2'
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40
gas/testsuite/gas/arm/mve-vmullbt-bad.s
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40
gas/testsuite/gas/arm/mve-vmullbt-bad.s
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@ -0,0 +1,40 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s32 q0, q1, q2
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.endr
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.endm
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.syntax unified
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.text
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.thumb
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vmullb.s64 q0, q1, q2
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vmullb.f16 q0, q1, q2
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vmullb.f32 q0, q1, q2
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vmullb.s32 q1, q1, q2
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vmullb.s32 q2, q1, q2
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cond vmullb
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vmullt.s64 q0, q1, q2
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vmullt.f16 q0, q1, q2
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vmullt.f32 q0, q1, q2
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vmullt.u32 q1, q1, q2
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vmullt.u32 q2, q1, q2
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cond vmullt
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it eq
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vmullbeq.s32 q0, q1, q2
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vmullbeq.s32 q0, q1, q2
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vpst
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vmullbeq.s32 q0, q1, q2
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vpst
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vmullb.s32 q0, q1, q2
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vmullbt.s32 q0, q1, q2
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it eq
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vmullteq.s32 q0, q1, q2
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vmullteq.s32 q0, q1, q2
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vpst
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vmullteq.s32 q0, q1, q2
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vpst
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vmullt.s32 q0, q1, q2
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vmulltt.s32 q0, q1, q2
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