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PowerPC: Support for Prefixed Add Immediate Shifted Instruction (RFC02686)
opcodes/ * ppc-opc.c (insert_si32, extract_si32, insert_nsi32, extract_nsi32): New functions. (SI32, NSI32, P_D_SI32_MASK, P_DRAPCREL_SI32_MASK): New macros. (IMM32): Update for new macros. (powerpc_opcodes): Add plis, paddis, psubis. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
This commit is contained in:
Surya Kumari Jangala
@@ -57,4 +57,39 @@ Disassembly of section \.text:
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.*: (d0 1e 22 f0|f0 22 1e d0) xxgfmul128gcm vs1,vs2,vs3
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.*: (d6 0f e0 f3|f3 e0 0f d6) xxgfmul128xts vs31,vs32,vs33
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.*: (d6 0f e0 f3|f3 e0 0f d6) xxgfmul128xts vs31,vs32,vs33
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.*: (06 00 00 00|00 00 00 06) paddis r12,r9,15
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.*: (3d 89 00 0f|0f 00 89 3d)
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.*: (06 00 00 00|00 00 00 06) paddis r12,r9,15
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.*: (3d 89 00 0f|0f 00 89 3d)
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.*: (06 00 ff ff|ff ff 00 06) paddis r12,r9,-32769
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.*: (3d 89 7f ff|ff 7f 89 3d)
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.*: (06 00 ff ff|ff ff 00 06) paddis r12,r9,-32769
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.*: (3d 89 7f ff|ff 7f 89 3d)
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.*: (06 10 00 00|00 00 10 06) paddis r9,0,25,1 # e4
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.*: (3d 20 00 19|19 00 20 3d)
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.*: (06 00 7f ff|ff 7f 00 06) plis r24,2147483647
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.*: (3f 00 ff ff|ff ff 00 3f)
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.*: (06 00 7f ff|ff 7f 00 06) plis r24,2147483647
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.*: (3f 00 ff ff|ff ff 00 3f)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (06 00 7f ff|ff 7f 00 06) plis r24,2147483647
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.*: (3f 00 ff ff|ff ff 00 3f)
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.*: (06 00 80 00|00 80 00 06) paddis r30,r10,-2147483648
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.*: (3f ca 00 00|00 00 ca 3f)
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.*: (06 00 80 00|00 80 00 06) paddis r30,r10,-2147483648
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.*: (3f ca 00 00|00 00 ca 3f)
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.*: (06 00 80 00|00 80 00 06) paddis r30,r10,-2147483648
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.*: (3f ca 00 00|00 00 ca 3f)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (06 00 7f ff|ff 7f 00 06) paddis r30,r10,2147483647
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.*: (3f ca ff ff|ff ff ca 3f)
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.*: (06 00 7f ff|ff 7f 00 06) paddis r30,r10,2147483647
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.*: (3f ca ff ff|ff ff ca 3f)
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.*: (06 00 7f ff|ff 7f 00 06) paddis r30,r10,2147483647
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.*: (3f ca ff ff|ff ff ca 3f)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (06 10 7f ff|ff 7f 10 06) paddis r15,0,2147483647,1 # 140
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.* (3d e0 ff ff|ff ff e0 3d)
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.*: (06 10 7f ff|ff 7f 10 06) paddis r15,0,2147483647,1 # 148
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.* (3d e0 ff ff|ff ff e0 3d)
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#pass
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@@ -49,3 +49,21 @@ _start:
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xxgfmul128gcm 1, 2, 3
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xxgfmul128 31, 32, 33, 1
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xxgfmul128xts 31, 32, 33
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paddis 12, 9, 15, 0
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paddis 12, 9, 15
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paddis 12, 9, ~(1<<15), 0
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paddis 12, 9, ~(1<<15)
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paddis 9, 0, 25, 1
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paddis 24, 0, 2147483647, 0
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paddis 24, 0, 2147483647
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plis 24, 2147483647
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paddis 30, 10, -2147483648, 0
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paddis 30, 10, -2147483648
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psubis 30, 10, 2147483648, 0
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nop
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paddis 30, 10, 2147483647, 0
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paddis 30, 10, 2147483647
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psubis 30, 10, -2147483647, 0
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paddis 15, 0, 2147483647, 1
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psubis 15, 0, -2147483647, 1
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@@ -691,6 +691,52 @@ extract_imm32 (uint64_t insn,
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return (insn & 0xffff) | ((insn >> 16) & 0xffff0000);
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}
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/* The 32bit SI field in a 64-bit D form prefix instruction when the field is split
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into separate SI0 and SI1 fields. */
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static uint64_t
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insert_si32 (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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const char **errmsg ATTRIBUTE_UNUSED)
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{
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return insn | ((value & 0xffff0000ULL) << 16) | (value & 0xffff);
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}
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static int64_t
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extract_si32 (uint64_t insn,
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ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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int *invalid ATTRIBUTE_UNUSED)
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{
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int64_t mask = 1ULL << 31;
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int64_t value = ((insn >> 16) & 0xffff0000ULL) | (insn & 0xffff);
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value = (value ^ mask) - mask;
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return value;
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}
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/* The NSI32 field in an 8-byte D form prefix instruction. This is the same
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as the SI32 field, only negated. The extraction function always marks it
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as invalid, since we never want to recognize an instruction which uses
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a field of this type. */
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static uint64_t
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insert_nsi32 (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect,
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const char **errmsg)
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{
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return insert_si32 (insn, -value, dialect, errmsg);
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}
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static int64_t
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extract_nsi32 (uint64_t insn,
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ppc_cpu_t dialect,
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int *invalid)
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{
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int64_t value = extract_si32 (insn, dialect, invalid);
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*invalid = 1;
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return -value;
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}
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/* The R field in an 8-byte prefix instruction when there are restrictions
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between R's value and the RA value (ie, they cannot both be non zero). */
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@@ -3073,8 +3119,18 @@ const struct powerpc_operand powerpc_operands[] =
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{ UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34,
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PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
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/* The 32bit SI field in an 8-byte D form prefix instruction. */
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#define SI32 NSI34 + 1
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{ UINT64_C(0xffffffff), PPC_OPSHIFT_INV, insert_si32, extract_si32, PPC_OPERAND_SIGNED },
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/* The NSI field in an 8-byte D form prefix instruction with 32bit SI field. This is
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the same as the SI32 field, only negated. */
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#define NSI32 SI32 + 1
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{ UINT64_C(0xffffffff), PPC_OPSHIFT_INV, insert_nsi32, extract_nsi32,
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PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
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/* The IMM32 field in a vector splat immediate prefix instruction. */
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#define IMM32 NSI34 + 1
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#define IMM32 NSI32 + 1
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{ 0xffffffff, PPC_OPSHIFT_INV, insert_imm32, extract_imm32, 0},
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/* The UIM field in a vector permute extended prefix instruction. */
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@@ -4031,9 +4087,15 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
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/* An 8-byte D form prefix instruction. */
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#define P_D_MASK (((-1ULL << 50) & ~PCREL_MASK) | OP_MASK)
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/* An 8-byte D form prefix instruction with 32bit SI field. */
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#define P_D_SI32_MASK (((-1ULL << 48) & ~PCREL_MASK) | OP_MASK)
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/* The same as P_D_MASK, but with the RA and PCREL fields specified. */
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#define P_DRAPCREL_MASK (P_D_MASK | PCREL_MASK | RA_MASK)
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/* The same as P_D_SI32_MASK, but with the RA and PCREL fields specified. */
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#define P_DRAPCREL_SI32_MASK (P_D_SI32_MASK | PCREL_MASK | RA_MASK)
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/* Mask for prefix X form instructions. */
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#define P_X_MASK (PREFIX_MASK | X_MASK)
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#define P_XX1_MASK (PREFIX_MASK | XX1_MASK)
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@@ -9863,6 +9925,9 @@ const struct powerpc_opcode prefix_opcodes[] = {
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{"pla", PMLS|OP(14), P_D_MASK, POWER10, EXT, {RT, D34, PRA0, PCREL1}},
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{"paddi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, SI34, PCREL}},
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{"psubi", PMLS|OP(14), P_D_MASK, POWER10, EXT, {RT, RA0, NSI34, PCREL}},
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{"plis", PMLS|OP(15), P_DRAPCREL_SI32_MASK, FUTURE, EXT, {RT, SI32}},
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{"paddis", PMLS|OP(15), P_D_SI32_MASK, FUTURE, 0, {RT, RA0, SI32, PCREL}},
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{"psubis", PMLS|OP(15), P_D_SI32_MASK, FUTURE, EXT, {RT, RA0, NSI32, PCREL}},
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{"xxsplti32dx", P8RR|VSOP(32,0), P_VSI_MASK, POWER10, 0, {XTS, IX, IMM32}},
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{"xxspltidp", P8RR|VSOP(32,2), P_VS_MASK, POWER10, 0, {XTS, IMM32}},
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{"xxspltiw", P8RR|VSOP(32,3), P_VS_MASK, POWER10, 0, {XTS, IMM32}},
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