Don't allow movabs with relocation in x32 mode.

gas/

2011-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (disallow_64bit_disp): New.
	(x86_elf_abi): Replace X86_64_LP64_ABI/X86_64_ILP32_ABI with
	X86_64_ABI/X86_64_X32_ABI.
	(md_assemble): Don't allow movabs with relocation in x32 mode.
	(i386_target_format): Updated.

gas/testsuite/

2011-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/ilp32/ilp32.exp: Run inval.

	* gas/i386/ilp32/inval.l: New.
	* gas/i386/ilp32/inval.s: Likewise.
	* gas/i386/ilp32/x86-64.s: Likewise.

	* gas/i386/ilp32/x86-64.d: Don't use ../x86_64.s.  Updated.
This commit is contained in:
H.J. Lu
2011-01-15 15:48:02 +00:00
parent 9d53781512
commit 7f56bc95d6
8 changed files with 383 additions and 22 deletions

View File

@ -1,3 +1,11 @@
2011-01-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (disallow_64bit_disp): New.
(x86_elf_abi): Replace X86_64_LP64_ABI/X86_64_ILP32_ABI with
X86_64_ABI/X86_64_X32_ABI.
(md_assemble): Don't allow movabs with relocation in x32 mode.
(i386_target_format): Updated.
2011-01-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (OPTION_N32): Renamed to ...

View File

@ -389,6 +389,7 @@ enum flag_code {
static enum flag_code flag_code;
static unsigned int object_64bit;
static unsigned int disallow_64bit_disp;
static int use_rela_relocations = 0;
#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
@ -399,8 +400,8 @@ static int use_rela_relocations = 0;
enum x86_elf_abi
{
I386_ABI,
X86_64_LP64_ABI,
X86_64_ILP32_ABI
X86_64_ABI,
X86_64_X32_ABI
};
static enum x86_elf_abi x86_elf_abi = I386_ABI;
@ -3005,10 +3006,21 @@ md_assemble (char *line)
/* Don't optimize displacement for movabs since it only takes 64bit
displacement. */
if (i.disp_operands
&& !i.disp32_encoding
&& (flag_code != CODE_64BIT
|| strcmp (mnemonic, "movabs") != 0))
optimize_disp ();
&& !i.disp32_encoding)
{
if (flag_code == CODE_64BIT)
{
if (strcmp (mnemonic, "movabs") == 0)
{
if (disallow_64bit_disp)
as_bad (_("'movabs' isn't supported in x32 mode"));
}
else
optimize_disp ();
}
else
optimize_disp ();
}
/* Next, we find a template that matches the given insn,
making sure the overlap of the given operands types is consistent
@ -8575,9 +8587,9 @@ i386_target_format (void)
{
update_code_flag (CODE_64BIT, 1);
if (default_arch[6] == '\0')
x86_elf_abi = X86_64_LP64_ABI;
x86_elf_abi = X86_64_ABI;
else
x86_elf_abi = X86_64_ILP32_ABI;
x86_elf_abi = X86_64_X32_ABI;
}
else if (!strcmp (default_arch, "i386"))
update_code_flag (CODE_32BIT, 1);
@ -8617,20 +8629,21 @@ i386_target_format (void)
default:
format = ELF_TARGET_FORMAT;
break;
case X86_64_LP64_ABI:
case X86_64_ABI:
use_rela_relocations = 1;
object_64bit = 1;
format = ELF_TARGET_FORMAT64;
break;
case X86_64_ILP32_ABI:
case X86_64_X32_ABI:
use_rela_relocations = 1;
object_64bit = 1;
disallow_64bit_disp = 1;
format = ELF_TARGET_FORMAT32;
break;
}
if (cpu_arch_isa == PROCESSOR_L1OM)
{
if (x86_elf_abi != X86_64_LP64_ABI)
if (x86_elf_abi != X86_64_ABI)
as_fatal (_("Intel L1OM is 64bit only"));
return ELF_TARGET_L1OM_FORMAT;
}

View File

@ -1,3 +1,13 @@
2011-01-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/ilp32.exp: Run inval.
* gas/i386/ilp32/inval.l: New.
* gas/i386/ilp32/inval.s: Likewise.
* gas/i386/ilp32/x86-64.s: Likewise.
* gas/i386/ilp32/x86-64.d: Don't use ../x86_64.s. Updated.
2011-01-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/cfi/ilp32.exp: Replace --n32 with --x32.

View File

@ -21,5 +21,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check] &&
}
}
run_list_test "inval" "-al"
set ASFLAGS "$old_ASFLAGS"
}

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@ -0,0 +1,20 @@
.*: Assembler messages:
.*:3: Error: .*
.*:4: Error: .*
GAS LISTING .*
[ ]*1[ ]+\.text
[ ]*2[ ]+\# All the following should be illegal for x32
[ ]*3[ ]+\?\?\?\? 48A10000 movabs xxx,%rax
\*\*\*\* Error:'movabs' isn't supported in x[ ]*32[ ]+mode
[ ]*3[ ]+00000000
[ ]*3[ ]+0000
[ ]*4[ ]+\?\?\?\? 48A10000 movabs foo,%rax
\*\*\*\* Error:'movabs' isn't supported in x[ ]*32[ ]+mode
[ ]*4[ ]+00000000
[ ]*4[ ]+0000
[ ]*5[ ]+
[ ]*6[ ]+\.data
[ ]*7[ ]+xxx:
[ ]*8[ ]+\?\?\?\? 00 \.byte 0

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@ -0,0 +1,8 @@
.text
# All the following should be illegal for x32
movabs xxx,%rax
movabs foo,%rax
.data
xxx:
.byte 0

View File

@ -1,4 +1,3 @@
#source: ../x86_64.s
#as: -J
#objdump: -dw
#name: x86-64 (ILP32)
@ -53,7 +52,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 41 03 00 add \(%r8\),%eax
[ ]*[a-f0-9]+: 45 03 00 add \(%r8\),%r8d
[ ]*[a-f0-9]+: 49 03 00 add \(%r8\),%rax
[ ]*[a-f0-9]+: 03 05 22 22 22 22 add 0x22222222\(%rip\),%eax # 222222c7 <foo\+0x222220c4>
[ ]*[a-f0-9]+: 03 05 22 22 22 22 add 0x22222222\(%rip\),%eax # 222222c7 <foo\+0x222220d6>
[ ]*[a-f0-9]+: 03 45 00 add 0x0\(%rbp\),%eax
[ ]*[a-f0-9]+: 03 04 25 22 22 22 22 add 0x22222222,%eax
[ ]*[a-f0-9]+: 41 03 45 00 add 0x0\(%r13\),%eax
@ -85,10 +84,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 83 04 81 11 addl \$0x11,\(%rcx,%rax,4\)
[ ]*[a-f0-9]+: 41 83 04 81 11 addl \$0x11,\(%r9,%rax,4\)
[ ]*[a-f0-9]+: 42 83 04 81 11 addl \$0x11,\(%rcx,%r8,4\)
[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 addl \$0x33,0x22222222\(%rip\) # 22222342 <foo\+0x2222213f>
[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 addq \$0x33,0x22222222\(%rip\) # 2222234a <foo\+0x22222147>
[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 addl \$0x33333333,0x22222222\(%rip\) # 22222354 <foo\+0x22222151>
[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 addq \$0x33333333,0x22222222\(%rip\) # 2222235f <foo\+0x2222215c>
[ ]*[a-f0-9]+: 83 05 22 22 22 22 33 addl \$0x33,0x22222222\(%rip\) # 22222342 <foo\+0x22222151>
[ ]*[a-f0-9]+: 48 83 05 22 22 22 22 33 addq \$0x33,0x22222222\(%rip\) # 2222234a <foo\+0x22222159>
[ ]*[a-f0-9]+: 81 05 22 22 22 22 33 33 33 33 addl \$0x33333333,0x22222222\(%rip\) # 22222354 <foo\+0x22222163>
[ ]*[a-f0-9]+: 48 81 05 22 22 22 22 33 33 33 33 addq \$0x33333333,0x22222222\(%rip\) # 2222235f <foo\+0x2222216e>
[ ]*[a-f0-9]+: 83 04 c5 22 22 22 22 33 addl \$0x33,0x22222222\(,%rax,8\)
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
[ ]*[a-f0-9]+: 83 80 22 22 22 22 33 addl \$0x33,0x22222222\(%rax\)
@ -111,20 +110,18 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 movabs 0x0,%eax
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 1d5 <bar\+0x2e>
[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 1cc <bar\+0x25>
[ ]*[a-f0-9]+: b0 00 mov \$0x0,%al
[ ]*[a-f0-9]+: 66 b8 00 00 mov \$0x0,%ax
[ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax
[ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 mov \$0x0,%rax
[ ]*[a-f0-9]+: a1 00 00 00 00 00 00 00 00 movabs 0x0,%eax
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 00 mov 0x0,%eax
[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%rax\),%eax
[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 203 <foo>
[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0\(%rip\),%eax # 1f1 <foo>
0+203 <foo>:
0+1f1 <foo>:
[ ]*[a-f0-9]+: a0 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%al
[ ]*[a-f0-9]+: 66 a1 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%ax
[ ]*[a-f0-9]+: a1 11 22 33 44 55 66 77 88 movabs 0x8877665544332211,%eax

View File

@ -0,0 +1,303 @@
.text
.intel_syntax noprefix
# REX prefix and addressing modes.
add edx,ecx
add edx,r9d
add r10d,ecx
add rdx,rcx
add r10,r9
add r8d,eax
add r8w,ax
add r8,rax
add eax,0x44332211
add rax,0xfffffffff4332211
add ax,0x4433
add rax,0x44332211
add dl,cl
add bh,dh
add dil,sil
add r15b,sil
add dil,r14b
add r15b,r14b
PUSH RAX
PUSH R8
POP R9
ADD AL,0x11
ADD AH,0x11
ADD SPL,0x11
ADD R8B,0x11
ADD R12B,0x11
MOV RAX,CR0
MOV R8,CR0
MOV RAX,CR8
MOV CR8,RAX
REP MOVSQ #[RSI],[RDI]
REP MOVSW #[RSI,[RDI]
REP MOVSQ #[RSI],[RDI]
MOV AL, 0x11
MOV AH, 0x11
MOV SPL, 0x11
MOV R12B, 0x11
MOV EAX,0x11223344
MOV R8D,0x11223344
MOV RAX,0x1122334455667788
MOV R8,0x1122334455667788
add eax,[rax]
ADD EAX,[R8]
ADD R8D,[R8]
ADD RAX,[R8]
ADD EAX,[0x22222222+RIP]
ADD EAX,[RBP+0x00]
ADD EAX,FLAT:[0x22222222]
ADD EAX,[R13+0]
ADD EAX,[RAX+RAX*4]
ADD EAX,[R8+RAX*4]
ADD R8D,[R8+RAX*4]
ADD EAX,[R8+R8*4]
ADD [RCX+R8*4],R8D
ADD EDX,[RAX+RAX*8]
ADD EDX,[RAX+RCX*8]
ADD EDX,[RAX+RDX*8]
ADD EDX,[RAX+RBX*8]
ADD EDX,[RAX]
ADD EDX,[RAX+RBP*8]
ADD EDX,[RAX+RSI*8]
ADD EDX,[RAX+RDI*8]
ADD EDX,[RAX+R8*8]
ADD EDX,[RAX+R9*8]
ADD EDX,[RAX+R10*8]
ADD EDX,[RAX+R11*8]
ADD EDX,[RAX+R12*8]
ADD EDX,[RAX+R13*8]
ADD EDX,[RAX+R14*8]
ADD EDX,[RAX+R15*8]
ADD ECX,0x11
ADD DWORD PTR [RAX],0x11
ADD QWORD PTR [RAX],0x11
ADD DWORD PTR [R8],0x11
ADD DWORD PTR [RCX+RAX*4],0x11
ADD DWORD PTR [R9+RAX*4],0x11
ADD DWORD PTR [RCX+R8*4],0x11
ADD DWORD PTR [0x22222222+RIP],0x33
ADD QWORD PTR [RIP+0x22222222],0x33
ADD DWORD PTR [RIP+0x22222222],0x33333333
ADD QWORD PTR [RIP+0x22222222],0x33333333
ADD DWORD PTR [RAX*8+0x22222222],0x33
ADD DWORD PTR [RAX+0x22222222],0x33
ADD DWORD PTR [RAX+0x22222222],0x33
ADD DWORD PTR [R8+RBP*8],0x33
ADD DWORD PTR FLAT:[0x22222222],0x33
#new instructions
MOV AL,FLAT:[0x8877665544332211]
MOV EAX,FLAT:[0x8877665544332211]
MOV FLAT:[0x8877665544332211],AL
MOV FLAT:[0x8877665544332211],EAX
MOV RAX,FLAT:[0x8877665544332211]
MOV FLAT:[0x8877665544332211],RAX
cqo
cdqe
movsx rax, eax
movsx rax, ax
movsx rax, al
bar:
.att_syntax
#testcase for symbol references.
#immediates - various sizes:
mov $symbol, %al
mov $symbol, %ax
mov $symbol, %eax
mov $symbol, %rax
#addressing modes:
#absolute 32bit addressing
mov symbol, %eax
#arithmetic
mov symbol(%rax), %eax
#RIP relative
mov symbol(%rip), %eax
.intel_syntax noprefix
#immediates - various sizes:
mov al, offset flat:symbol
mov ax, offset flat:symbol
mov eax, offset flat:symbol
mov rax, offset flat:symbol
#parts aren't supported by the parser, yet (and not at all for symbol refs)
#mov eax, high part symbol
#mov eax, low part symbol
#addressing modes
#absolute 32bit addressing
mov eax, [symbol]
#arithmetic
mov eax, [rax+symbol]
#RIP relative
mov eax, [rip+symbol]
foo:
.att_syntax
#absolute 64bit addressing
mov 0x8877665544332211,%al
mov 0x8877665544332211,%ax
mov 0x8877665544332211,%eax
mov 0x8877665544332211,%rax
mov %al,0x8877665544332211
mov %ax,0x8877665544332211
mov %eax,0x8877665544332211
mov %rax,0x8877665544332211
movb 0x8877665544332211,%al
movw 0x8877665544332211,%ax
movl 0x8877665544332211,%eax
movq 0x8877665544332211,%rax
movb %al,0x8877665544332211
movw %ax,0x8877665544332211
movl %eax,0x8877665544332211
movq %rax,0x8877665544332211
#absolute signed 32bit addressing
mov 0xffffffffff332211,%al
mov 0xffffffffff332211,%ax
mov 0xffffffffff332211,%eax
mov 0xffffffffff332211,%rax
mov %al,0xffffffffff332211
mov %ax,0xffffffffff332211
mov %eax,0xffffffffff332211
mov %rax,0xffffffffff332211
movb 0xffffffffff332211,%al
movw 0xffffffffff332211,%ax
movl 0xffffffffff332211,%eax
movq 0xffffffffff332211,%rax
movb %al,0xffffffffff332211
movw %ax,0xffffffffff332211
movl %eax,0xffffffffff332211
movq %rax,0xffffffffff332211
cmpxchg16b (%rax)
.intel_syntax noprefix
cmpxchg16b oword ptr [rax]
.att_syntax
movsx %al, %si
movsx %al, %esi
movsx %al, %rsi
movsx %ax, %esi
movsx %ax, %rsi
movsx %eax, %rsi
movsx (%rax), %edx
movsx (%rax), %rdx
movsx (%rax), %dx
movsbl (%rax), %edx
movsbq (%rax), %rdx
movsbw (%rax), %dx
movswl (%rax), %edx
movswq (%rax), %rdx
movzx %al, %si
movzx %al, %esi
movzx %al, %rsi
movzx %ax, %esi
movzx %ax, %rsi
movzx (%rax), %edx
movzx (%rax), %rdx
movzx (%rax), %dx
movzb (%rax), %edx
movzb (%rax), %rdx
movzb (%rax), %dx
movzbl (%rax), %edx
movzbq (%rax), %rdx
movzbw (%rax), %dx
movzwl (%rax), %edx
movzwq (%rax), %rdx
.intel_syntax noprefix
movsx si,al
movsx esi,al
movsx rsi,al
movsx esi,ax
movsx rsi,ax
movsx rsi,eax
movsx edx,BYTE PTR [rax]
movsx rdx,BYTE PTR [rax]
movsx dx,BYTE PTR [rax]
movsx edx,WORD PTR [rax]
movsx rdx,WORD PTR [rax]
movzx si,al
movzx esi,al
movzx rsi,al
movzx esi,ax
movzx rsi,ax
movzx edx,BYTE PTR [rax]
movzx rdx,BYTE PTR [rax]
movzx dx,BYTE PTR [rax]
movzx edx,WORD PTR [rax]
movzx rdx,WORD PTR [rax]
movq xmm1,QWORD PTR [rsp]
movq xmm1,[rsp]
movq QWORD PTR [rsp],xmm1
movq [rsp],xmm1
.att_syntax
fnstsw
fnstsw %ax
fstsw
fstsw %ax
.intel_syntax noprefix
fnstsw
fnstsw ax
fstsw
fstsw ax
.att_syntax
movsx (%rax),%ax
movsx (%rax),%eax
movsx (%rax),%rax
movsxb (%rax), %dx
movsxb (%rax), %edx
movsxb (%rax), %rdx
movsxw (%rax), %edx
movsxw (%rax), %rdx
movsxl (%rax), %rdx
movsxd (%rax),%rax
movzx (%rax),%ax
movzx (%rax),%eax
movzx (%rax),%rax
movzxb (%rax), %dx
movzxb (%rax), %edx
movzxb (%rax), %rdx
movzxw (%rax), %edx
movzxw (%rax), %rdx
movnti %eax, (%rax)
movntil %eax, (%rax)
movnti %rax, (%rax)
movntiq %rax, (%rax)
.intel_syntax noprefix
movsx ax, BYTE PTR [rax]
movsx eax, BYTE PTR [rax]
movsx eax, WORD PTR [rax]
movsx rax, WORD PTR [rax]
movsx rax, DWORD PTR [rax]
movsxd rax, [rax]
movzx ax, BYTE PTR [rax]
movzx eax, BYTE PTR [rax]
movzx eax, WORD PTR [rax]
movzx rax, WORD PTR [rax]
movnti dword ptr [rax], eax
movnti qword ptr [rax], rax