mirror of
https://github.com/espressif/binutils-gdb.git
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Thu Dec 10 18:39:46 1998 Dave Brolley <brolley@cygnus.com>
* fr30-opc.c,fr30-opc.h: Regenerated.
This commit is contained in:
Dave Brolley
@ -1,3 +1,9 @@
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start-sanitize-fr30
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Thu Dec 10 18:39:46 1998 Dave Brolley <brolley@cygnus.com>
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* fr30-opc.c,fr30-opc.h: Regenerated.
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end-sanitize-fr30
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Thu Dec 10 12:49:24 1998 Doug Evans <devans@canuck.cygnus.com>
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* m32r-opc.c: Regenerate.
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@ -389,6 +389,9 @@ static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
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{ HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_TBIT, & HW_ENT (HW_H_TBIT + 1), "h-tbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_D0BIT, & HW_ENT (HW_H_D0BIT + 1), "h-d0bit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_D1BIT, & HW_ENT (HW_H_D1BIT + 1), "h-d1bit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
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{ HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
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{ HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
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@ -560,24 +563,33 @@ const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
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/* ccc: coprocessor calc */
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{ "ccc", & HW_ENT (HW_H_UINT), 0, 8,
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{ 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
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/* nbit: negative bit */
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/* nbit: negative bit */
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{ "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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/* vbit: overflow bit */
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/* vbit: overflow bit */
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{ "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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/* zbit: zero bit */
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/* zbit: zero bit */
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{ "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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/* cbit: carry bit */
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/* cbit: carry bit */
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{ "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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/* ibit: interrupt bit */
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/* ibit: interrupt bit */
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{ "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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/* sbit: stack bit */
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/* sbit: stack bit */
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{ "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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/* tbit: trace trap bit */
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{ "tbit", & HW_ENT (HW_H_TBIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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/* d0bit: division 0 bit */
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{ "d0bit", & HW_ENT (HW_H_D0BIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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/* d1bit: division 1 bit */
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{ "d1bit", & HW_ENT (HW_H_D1BIT), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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/* ccr: condition code bits */
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{ "ccr", & HW_ENT (HW_H_CCR), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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@ -782,6 +794,62 @@ static const CGEN_OPERAND_INSTANCE fmt_mulh_ops[] = {
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{ 0 }
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};
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static const CGEN_OPERAND_INSTANCE fmt_div0s_ops[] = {
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{ INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
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{ INPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
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{ INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
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{ OUTPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
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{ OUTPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
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{ OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
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{ 0 }
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};
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static const CGEN_OPERAND_INSTANCE fmt_div0u_ops[] = {
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{ OUTPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
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{ OUTPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
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{ OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
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{ 0 }
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};
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static const CGEN_OPERAND_INSTANCE fmt_div1_ops[] = {
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{ INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
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{ INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
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{ INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
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{ INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
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{ INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
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{ INPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
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{ OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
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{ OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
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{ OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
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{ OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
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{ 0 }
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};
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static const CGEN_OPERAND_INSTANCE fmt_div2_ops[] = {
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{ INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
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{ INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
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{ INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
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{ INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
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{ OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
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{ OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, COND_REF },
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{ OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
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{ 0 }
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};
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static const CGEN_OPERAND_INSTANCE fmt_div3_ops[] = {
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{ INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
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{ INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
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{ OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
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{ 0 }
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};
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static const CGEN_OPERAND_INSTANCE fmt_div4s_ops[] = {
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{ INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
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{ INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
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{ OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
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{ 0 }
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};
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static const CGEN_OPERAND_INSTANCE fmt_lsl_ops[] = {
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{ INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
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{ INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
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@ -1508,10 +1576,26 @@ static const CGEN_IFMT fmt_div0s = {
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16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
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};
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static const CGEN_IFMT fmt_div0u = {
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16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
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};
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static const CGEN_IFMT fmt_div1 = {
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16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
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};
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static const CGEN_IFMT fmt_div2 = {
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16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
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};
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static const CGEN_IFMT fmt_div3 = {
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16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
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};
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static const CGEN_IFMT fmt_div4s = {
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16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
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};
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static const CGEN_IFMT fmt_lsl = {
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16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
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};
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@ -1788,6 +1872,10 @@ static const CGEN_IFMT fmt_copst = {
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16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
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};
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static const CGEN_IFMT fmt_nop = {
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16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
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};
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static const CGEN_IFMT fmt_andccr = {
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16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
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};
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@ -2199,7 +2287,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
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FR30_INSN_DIV0S, "div0s", "div0s",
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{ { MNEM, ' ', OP (RI), 0 } },
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& fmt_div0s, { 0x9740 },
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(PTR) 0,
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(PTR) & fmt_div0s_ops[0],
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{ 0, 0, { 0 } }
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},
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/* div0u $Ri */
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@ -2207,8 +2295,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
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{ 1, 1, 1, 1 },
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FR30_INSN_DIV0U, "div0u", "div0u",
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{ { MNEM, ' ', OP (RI), 0 } },
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& fmt_div0s, { 0x9750 },
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(PTR) 0,
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& fmt_div0u, { 0x9750 },
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(PTR) & fmt_div0u_ops[0],
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{ 0, 0, { 0 } }
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},
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/* div1 $Ri */
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@ -2216,8 +2304,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
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{ 1, 1, 1, 1 },
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FR30_INSN_DIV1, "div1", "div1",
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{ { MNEM, ' ', OP (RI), 0 } },
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& fmt_div0s, { 0x9760 },
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(PTR) 0,
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& fmt_div1, { 0x9760 },
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(PTR) & fmt_div1_ops[0],
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{ 0, 0, { 0 } }
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},
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/* div2 $Ri */
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@ -2225,8 +2313,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
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{ 1, 1, 1, 1 },
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FR30_INSN_DIV2, "div2", "div2",
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{ { MNEM, ' ', OP (RI), 0 } },
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& fmt_div0s, { 0x9770 },
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(PTR) 0,
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& fmt_div2, { 0x9770 },
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(PTR) & fmt_div2_ops[0],
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{ 0, 0, { 0 } }
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},
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/* div3 */
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@ -2235,7 +2323,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
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FR30_INSN_DIV3, "div3", "div3",
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{ { MNEM, 0 } },
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& fmt_div3, { 0x9f60 },
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(PTR) 0,
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(PTR) & fmt_div3_ops[0],
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{ 0, 0, { 0 } }
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},
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/* div4s */
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@ -2243,8 +2331,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
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{ 1, 1, 1, 1 },
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FR30_INSN_DIV4S, "div4s", "div4s",
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{ { MNEM, 0 } },
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& fmt_div3, { 0x9f70 },
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(PTR) 0,
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& fmt_div4s, { 0x9f70 },
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(PTR) & fmt_div4s_ops[0],
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{ 0, 0, { 0 } }
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},
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/* lsl $Rj,$Ri */
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@ -3206,7 +3294,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
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{ 1, 1, 1, 1 },
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FR30_INSN_NOP, "nop", "nop",
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{ { MNEM, 0 } },
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& fmt_div3, { 0x9fa0 },
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& fmt_nop, { 0x9fa0 },
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(PTR) 0,
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{ 0, 0, { 0 } }
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},
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@ -156,8 +156,9 @@ typedef enum cgen_operand_type {
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, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
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, FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
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, FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
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, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_CCR
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, FR30_OPERAND_SCR, FR30_OPERAND_ILM, FR30_OPERAND_MAX
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, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
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, FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
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, FR30_OPERAND_ILM, FR30_OPERAND_MAX
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} CGEN_OPERAND_TYPE;
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/* Non-boolean attributes. */
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@ -346,8 +347,9 @@ typedef enum hw_type {
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, HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR
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, HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
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, HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
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, HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_CCR
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, HW_H_SCR, HW_H_ILM, HW_MAX
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, HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
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, HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
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, HW_H_ILM, HW_MAX
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} HW_TYPE;
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#define MAX_HW ((int) HW_MAX)
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