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[AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_reg

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Use a macro to define 31 regular registers followed by a supplied
value for 0b11111.  The SVE code will also use this for vector base
and offset registers.

opcodes/
	* aarch64-opc.c (BANK): New macro.
	(R32, R64): Take a register number as argument
	(int_reg): Use BANK.
This commit is contained in:
Richard Sandiford
2016-09-21 16:51:37 +01:00
parent 8a7f0c1b5a
commit 72e9f31937
2 changed files with 17 additions and 18 deletions
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6
opcodes/ChangeLog
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@ -1,3 +1,9 @@
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-opc.c (BANK): New macro.
(R32, R64): Take a register number as argument
(int_reg): Use BANK.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-opc.c (print_register_list): Add a prefix parameter.

29
opcodes/aarch64-opc.c
View File

@ -2149,32 +2149,25 @@ aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd oper
return -1;
}
/* R0...R30, followed by FOR31. */
#define BANK(R, FOR31) \
{ R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
/* [0][0] 32-bit integer regs with sp Wn
[0][1] 64-bit integer regs with sp Xn sf=1
[1][0] 32-bit integer regs with #0 Wn
[1][1] 64-bit integer regs with #0 Xn sf=1 */
static const char *int_reg[2][2][32] = {
#define R32 "w"
#define R64 "x"
{ { R32 "0", R32 "1", R32 "2", R32 "3", R32 "4", R32 "5", R32 "6", R32 "7",
R32 "8", R32 "9", R32 "10", R32 "11", R32 "12", R32 "13", R32 "14", R32 "15",
R32 "16", R32 "17", R32 "18", R32 "19", R32 "20", R32 "21", R32 "22", R32 "23",
R32 "24", R32 "25", R32 "26", R32 "27", R32 "28", R32 "29", R32 "30", "wsp" },
{ R64 "0", R64 "1", R64 "2", R64 "3", R64 "4", R64 "5", R64 "6", R64 "7",
R64 "8", R64 "9", R64 "10", R64 "11", R64 "12", R64 "13", R64 "14", R64 "15",
R64 "16", R64 "17", R64 "18", R64 "19", R64 "20", R64 "21", R64 "22", R64 "23",
R64 "24", R64 "25", R64 "26", R64 "27", R64 "28", R64 "29", R64 "30", "sp" } },
{ { R32 "0", R32 "1", R32 "2", R32 "3", R32 "4", R32 "5", R32 "6", R32 "7",
R32 "8", R32 "9", R32 "10", R32 "11", R32 "12", R32 "13", R32 "14", R32 "15",
R32 "16", R32 "17", R32 "18", R32 "19", R32 "20", R32 "21", R32 "22", R32 "23",
R32 "24", R32 "25", R32 "26", R32 "27", R32 "28", R32 "29", R32 "30", R32 "zr" },
{ R64 "0", R64 "1", R64 "2", R64 "3", R64 "4", R64 "5", R64 "6", R64 "7",
R64 "8", R64 "9", R64 "10", R64 "11", R64 "12", R64 "13", R64 "14", R64 "15",
R64 "16", R64 "17", R64 "18", R64 "19", R64 "20", R64 "21", R64 "22", R64 "23",
R64 "24", R64 "25", R64 "26", R64 "27", R64 "28", R64 "29", R64 "30", R64 "zr" } }
#define R32(X) "w" #X
#define R64(X) "x" #X
{ BANK (R32, "wsp"), BANK (R64, "sp") },
{ BANK (R32, "wzr"), BANK (R64, "xzr") }
#undef R64
#undef R32
};
#undef BANK
/* Return the integer register name.
if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */