mirror of
https://github.com/espressif/binutils-gdb.git
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aarch64: Add the SVE BFMLSL instructions
This patch adds the SVE BFMLSLB and BFMLSLT instructions, which are available when FEAT_SME2 is implemented.
This commit is contained in:
Richard Sandiford
3
gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.d
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@@ -0,0 +1,3 @@
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#as: -march=armv8-a+sme2
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#source: sve2-sme2-3-invalid.s
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#error_output: sve2-sme2-3-invalid.l
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17
gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.l
Normal file
17
gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.l
Normal file
@@ -0,0 +1,17 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bfmlslb 0,z0\.h,z0\.h\[0\]'
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlslb z0\.s,0,z0\.h\[0\]'
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bfmlslb z0\.s,z0\.h,0'
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[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlslb z0\.s,z0\.h,z8\.h\[0\]'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlslb z0\.s,z0\.h,z0\.h\[-1\]'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlslb z0\.s,z0\.h,z0\.h\[8\]'
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[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlslb z0\.h,z0\.h,z0\.h\[0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: bfmlslb z0\.s, z0\.h, z0\.h\[0\]
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[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlslb z0\.d,z0\.h,z0\.h\[0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: bfmlslb z0\.s, z0\.h, z0\.h\[0\]
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[^ :]+:[0-9]+: Warning: output register of preceding `movprfx' used as input at operand 2 -- `bfmlslb z0\.s,z0\.h,z1\.h\[0\]'
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[^ :]+:[0-9]+: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `bfmlslb z0\.s,z1\.h,z2\.h\[0\]'
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[^ :]+:[0-9]+: Warning: predicated instruction expected after `movprfx' -- `bfmlslb z0\.s,z1\.h,z2\.h\[0\]'
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[^ :]+:[0-9]+: Warning: predicated instruction expected after `movprfx' -- `bfmlslb z0\.s,z1\.h,z2\.h\[0\]'
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15
gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.s
Normal file
15
gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.s
Normal file
@@ -0,0 +1,15 @@
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bfmlslb 0, z0.h, z0.h[0]
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bfmlslb z0.s, 0, z0.h[0]
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bfmlslb z0.s, z0.h, 0
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bfmlslb z0.s, z0.h, z8.h[0]
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bfmlslb z0.s, z0.h, z0.h[-1]
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bfmlslb z0.s, z0.h, z0.h[8]
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bfmlslb z0.h, z0.h, z0.h[0]
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bfmlslb z0.d, z0.h, z0.h[0]
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movprfx z0, z1; bfmlslb z0.s, z0.h, z1.h[0]
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movprfx z0, z1; bfmlslb z0.s, z1.h, z0.h[0]
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movprfx z3, z4; bfmlslb z0.s, z1.h, z2.h[0]
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movprfx z0.s, p0/m, z1.s; bfmlslb z0.s, z1.h, z2.h[0]
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movprfx z0.s, p0/z, z1.s; bfmlslb z0.s, z1.h, z2.h[0]
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3
gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.d
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@@ -0,0 +1,3 @@
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#as: -march=armv8-a+sme
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#source: sve2-sme2-3.s
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#error_output: sve2-sme2-3-noarch.l
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29
gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.l
Normal file
29
gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.l
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@@ -0,0 +1,29 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z0\.h,z0\.h\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb Z0\.S,Z0\.H,Z0\.H\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z31\.s,z0\.h,z0\.h\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z31\.h,z0\.h\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z0\.h,z7\.h\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z0\.h,z0\.h\[7\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z5\.s,z22\.h,z4\.h\[3\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z1\.h,z1\.h\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z0\.h,z0\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z31\.s,z0\.h,z0\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z31\.h,z0\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z0\.h,z31\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z25\.s,z13\.h,z6\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslb z0\.s,z1\.h,z2\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z0\.h,z0\.h\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt Z0\.S,Z0\.H,Z0\.H\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z31\.s,z0\.h,z0\.h\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z31\.h,z0\.h\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z0\.h,z7\.h\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z0\.h,z0\.h\[7\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z5\.s,z22\.h,z4\.h\[3\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z1\.h,z1\.h\[0\]'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z0\.h,z0\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z31\.s,z0\.h,z0\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z31\.h,z0\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z0\.h,z31\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z25\.s,z13\.h,z6\.h'
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[^ :]+:[0-9]+: Error: selected processor does not support `bfmlslt z0\.s,z1\.h,z2\.h'
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41
gas/testsuite/gas/aarch64/sve2-sme2-3.d
Normal file
41
gas/testsuite/gas/aarch64/sve2-sme2-3.d
Normal file
@@ -0,0 +1,41 @@
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#as: -march=armv8-a+sme2
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#objdump: -dr
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[^:]+: file format .*
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[^:]+:
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[^:]+:
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[^:]+: 64e06000 bfmlslb z0\.s, z0\.h, z0\.h\[0\]
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[^:]+: 64e06000 bfmlslb z0\.s, z0\.h, z0\.h\[0\]
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[^:]+: 64e0601f bfmlslb z31\.s, z0\.h, z0\.h\[0\]
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[^:]+: 64e063e0 bfmlslb z0\.s, z31\.h, z0\.h\[0\]
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[^:]+: 64e76000 bfmlslb z0\.s, z0\.h, z7\.h\[0\]
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[^:]+: 64f86800 bfmlslb z0\.s, z0\.h, z0\.h\[7\]
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[^:]+: 64ec6ac5 bfmlslb z5\.s, z22\.h, z4\.h\[3\]
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[^:]+: 0420bc20 movprfx z0, z1
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[^:]+: 64e16020 bfmlslb z0\.s, z1\.h, z1\.h\[0\]
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[^:]+: 64e0a000 bfmlslb z0\.s, z0\.h, z0\.h
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[^:]+: 64e0a01f bfmlslb z31\.s, z0\.h, z0\.h
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[^:]+: 64e0a3e0 bfmlslb z0\.s, z31\.h, z0\.h
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[^:]+: 64ffa000 bfmlslb z0\.s, z0\.h, z31\.h
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[^:]+: 64e6a1b9 bfmlslb z25\.s, z13\.h, z6\.h
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[^:]+: 0420bc20 movprfx z0, z1
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[^:]+: 64e2a020 bfmlslb z0\.s, z1\.h, z2\.h
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[^:]+: 64e06400 bfmlslt z0\.s, z0\.h, z0\.h\[0\]
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[^:]+: 64e06400 bfmlslt z0\.s, z0\.h, z0\.h\[0\]
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[^:]+: 64e0641f bfmlslt z31\.s, z0\.h, z0\.h\[0\]
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[^:]+: 64e067e0 bfmlslt z0\.s, z31\.h, z0\.h\[0\]
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[^:]+: 64e76400 bfmlslt z0\.s, z0\.h, z7\.h\[0\]
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[^:]+: 64f86c00 bfmlslt z0\.s, z0\.h, z0\.h\[7\]
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[^:]+: 64ec6ec5 bfmlslt z5\.s, z22\.h, z4\.h\[3\]
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[^:]+: 0420bc20 movprfx z0, z1
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[^:]+: 64e16420 bfmlslt z0\.s, z1\.h, z1\.h\[0\]
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[^:]+: 64e0a400 bfmlslt z0\.s, z0\.h, z0\.h
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[^:]+: 64e0a41f bfmlslt z31\.s, z0\.h, z0\.h
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[^:]+: 64e0a7e0 bfmlslt z0\.s, z31\.h, z0\.h
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[^:]+: 64ffa400 bfmlslt z0\.s, z0\.h, z31\.h
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[^:]+: 64e6a5b9 bfmlslt z25\.s, z13\.h, z6\.h
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[^:]+: 0420bc20 movprfx z0, z1
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[^:]+: 64e2a420 bfmlslt z0\.s, z1\.h, z2\.h
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35
gas/testsuite/gas/aarch64/sve2-sme2-3.s
Normal file
35
gas/testsuite/gas/aarch64/sve2-sme2-3.s
Normal file
@@ -0,0 +1,35 @@
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bfmlslb z0.s, z0.h, z0.h[0]
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BFMLSLB Z0.S, Z0.H, Z0.H[0]
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bfmlslb z31.s, z0.h, z0.h[0]
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bfmlslb z0.s, z31.h, z0.h[0]
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bfmlslb z0.s, z0.h, z7.h[0]
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bfmlslb z0.s, z0.h, z0.h[7]
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bfmlslb z5.s, z22.h, z4.h[3]
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movprfx z0, z1; bfmlslb z0.s, z1.h, z1.h[0]
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bfmlslb z0.s, z0.h, z0.h
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bfmlslb z31.s, z0.h, z0.h
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bfmlslb z0.s, z31.h, z0.h
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bfmlslb z0.s, z0.h, z31.h
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bfmlslb z25.s, z13.h, z6.h
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movprfx z0, z1; bfmlslb z0.s, z1.h, z2.h
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bfmlslt z0.s, z0.h, z0.h[0]
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BFMLSLT Z0.S, Z0.H, Z0.H[0]
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bfmlslt z31.s, z0.h, z0.h[0]
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bfmlslt z0.s, z31.h, z0.h[0]
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bfmlslt z0.s, z0.h, z7.h[0]
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bfmlslt z0.s, z0.h, z0.h[7]
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bfmlslt z5.s, z22.h, z4.h[3]
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movprfx z0, z1; bfmlslt z0.s, z1.h, z1.h[0]
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bfmlslt z0.s, z0.h, z0.h
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bfmlslt z31.s, z0.h, z0.h
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bfmlslt z0.s, z31.h, z0.h
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bfmlslt z0.s, z0.h, z31.h
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bfmlslt z25.s, z13.h, z6.h
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movprfx z0, z1; bfmlslt z0.s, z1.h, z2.h
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File diff suppressed because it is too large
Load Diff
@@ -2728,6 +2728,9 @@ static const aarch64_feature_set aarch64_feature_cssc =
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#define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \
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F_STRICT | FLAGS, 0, TIED, NULL }
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#define SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \
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FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
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#define SME2_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SME2_I16I64, OPS, QUALS, \
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F_STRICT | FLAGS, 0, TIED, NULL }
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@@ -5357,6 +5360,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
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SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
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/* SME2 extensions to SVE2. */
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SME2_INSNC ("bfmlslb", 0x64e06000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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SME2_INSNC ("bfmlslb", 0x64e0a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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SME2_INSNC ("bfmlslt", 0x64e06400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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SME2_INSNC ("bfmlslt", 0x64e0a400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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SME2_INSN ("whilege", 0x25205010, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
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SME2_INSN ("whilegt", 0x25205011, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
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SME2_INSN ("whilehi", 0x25205811, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
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