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bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64}
This patch adds support for the BPF V4 ISA byte swap instructions to
opcodes, assembler and disassembler.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_IMM32_BSWAP16): Define.
(BPF_IMM32_BSWAP32): Likewise.
(BPF_IMM32_BSWAP64): Likewise.
(enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}.
opcodes/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
instructions.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions.
* testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions.
* testsuite/gas/bpf/alu.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
This commit is contained in:
Jose E. Marchesi
@ -1,3 +1,13 @@
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2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
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* doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions.
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* testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions.
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* testsuite/gas/bpf/alu.d: Likewise.
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* testsuite/gas/bpf/alu-be.d: Likewise.
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* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
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* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
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* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
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2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
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* doc/c-bpf.texi (BPF Instructions): The pseudoc syntax for MOVS*
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@ -404,6 +404,26 @@ Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian
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and store it back in @code{rd}.
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@end table
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@subsection Byte swap instructions
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@table @code
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@item bswap rd, 16
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@itemx rd = bswap16 rd
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Swap the least-significant 16-bit word in @code{rd} with the
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most-significant 16-bit word.
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@item bswap rd, 32
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@itemx rd = bswap32 rd
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Swap the least-significant 32-bit word in @code{rd} with the
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most-significant 32-bit word.
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@item bswap rd, 64
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@itemx rd = bswap64 rd
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Swap the least-significant 64-bit word in @code{rd} with the
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most-significant 64-bit word.
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@end table
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@subsection 64-bit load and pseudo maps
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@table @code
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@ -66,3 +66,6 @@ Disassembly of section .text:
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1b8: bf 12 00 08 00 00 00 00 r1 = \(s8\) r2
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1c0: bf 12 00 10 00 00 00 00 r1 = \(s16\) r2
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1c8: bf 12 00 20 00 00 00 00 r1 = \(s32\) r2
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1d0: d7 10 00 00 00 00 00 10 r1 = bswap16 r1
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1d8: d7 20 00 00 00 00 00 20 r2 = bswap32 r2
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1e0: d7 30 00 00 00 00 00 40 r3 = bswap64 r3
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@ -66,3 +66,6 @@ Disassembly of section .text:
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1b8: bf 12 00 08 00 00 00 00 movs %r1,%r2,8
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1c0: bf 12 00 10 00 00 00 00 movs %r1,%r2,16
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1c8: bf 12 00 20 00 00 00 00 movs %r1,%r2,32
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1d0: d7 10 00 00 00 00 00 10 bswap %r1,16
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1d8: d7 20 00 00 00 00 00 20 bswap %r2,32
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1e0: d7 30 00 00 00 00 00 40 bswap %r3,64
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@ -66,3 +66,6 @@ Disassembly of section .text:
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1b8: bf 21 08 00 00 00 00 00 r1 = \(s8\) r2
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1c0: bf 21 10 00 00 00 00 00 r1 = \(s16\) r2
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1c8: bf 21 20 00 00 00 00 00 r1 = \(s32\) r2
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1d0: d7 01 00 00 10 00 00 00 r1 = bswap16 r1
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1d8: d7 02 00 00 20 00 00 00 r2 = bswap32 r2
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1e0: d7 03 00 00 40 00 00 00 r3 = bswap64 r3
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@ -58,3 +58,6 @@
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r1 = (s8) r2
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r1 = (s16) r2
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r1 = (s32) r2
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r1 = bswap16 r1
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r2 = bswap32 r2
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r3 = bswap64 r3
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@ -66,3 +66,6 @@ Disassembly of section .text:
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1b8: bf 21 08 00 00 00 00 00 movs %r1,%r2,8
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1c0: bf 21 10 00 00 00 00 00 movs %r1,%r2,16
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1c8: bf 21 20 00 00 00 00 00 movs %r1,%r2,32
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1d0: d7 01 00 00 10 00 00 00 bswap %r1,16
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1d8: d7 02 00 00 20 00 00 00 bswap %r2,32
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1e0: d7 03 00 00 40 00 00 00 bswap %r3,64
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@ -58,3 +58,6 @@
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movs %r1,%r2,8
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movs %r1,%r2,16
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movs %r1,%r2,32
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bswap %r1, 16
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bswap %r2, 32
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bswap %r3, 64
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@ -1,3 +1,10 @@
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2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
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* opcode/bpf.h (BPF_IMM32_BSWAP16): Define.
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(BPF_IMM32_BSWAP32): Likewise.
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(BPF_IMM32_BSWAP64): Likewise.
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(enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}.
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2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
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* opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL.
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@ -140,6 +140,10 @@ typedef uint64_t bpf_insn_word;
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#define BPF_IMM32_END32 ((uint64_t)0x00000020)
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#define BPF_IMM32_END64 ((uint64_t)0x00000040)
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#define BPF_IMM32_BSWAP16 ((uint64_t)0x00000010)
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#define BPF_IMM32_BSWAP32 ((uint64_t)0x00000020)
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#define BPF_IMM32_BSWAP64 ((uint64_t)0x00000040)
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#define BPF_IMM32_AADD ((uint64_t)0x00000000)
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#define BPF_IMM32_AOR ((uint64_t)0x00000040)
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#define BPF_IMM32_AAND ((uint64_t)0x00000050)
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@ -178,6 +182,8 @@ enum bpf_insn_id
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BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I,
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BPF_INSN_MOVS328R, BPF_INSN_MOVS3216R, BPF_INSN_MOVS3232R,
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BPF_INSN_MOV32R, BPF_INSN_MOV32I,
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/* Byte swap instructions. */
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BPF_INSN_BSWAP16, BPF_INSN_BSWAP32, BPF_INSN_BSWAP64,
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/* Endianness conversion instructions. */
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BPF_INSN_ENDLE16, BPF_INSN_ENDLE32, BPF_INSN_ENDLE64,
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BPF_INSN_ENDBE16, BPF_INSN_ENDBE32, BPF_INSN_ENDBE64,
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@ -1,3 +1,8 @@
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2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
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* bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
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instructions.
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2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
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* bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
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@ -182,6 +182,14 @@ const struct bpf_opcode bpf_opcodes[] =
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{BPF_INSN_ENDBE64, "endbe%W%dr , 64", "%dr = be64%w%dr",
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BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END64},
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/* Byte-swap instructions. */
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{BPF_INSN_BSWAP16, "bswap%W%dr , 16", "%dr%w=%wbswap16%w%dr",
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BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU64|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_BSWAP16},
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{BPF_INSN_BSWAP32, "bswap%W%dr , 32", "%dr%w=%wbswap32%w%dr",
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BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU64|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_BSWAP32},
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{BPF_INSN_BSWAP64, "bswap%W%dr , 64", "%dr%w=%wbswap64%w%dr",
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BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU64|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_BSWAP64},
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/* 64-bit load instruction. */
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{BPF_INSN_LDDW, "lddw%W%dr , %i64", "%dr = %i64%wll",
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BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_IMM},
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