mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-07-26 11:22:28 +08:00
* gas/config/tc-arm.c (do_t_it): Fully initialise now_it.
(new_automatic_it_block): Likewise. (handle_it_block): Record whether current instruction is conditionally executed. * gas/config/tc-arm.c (depr_insn_mask): New structure. (depr_it_insns): New variable. (it_fsm_post_encode): Warn on deprecated uses. * gas/config/tc-arm.h (current_it): Add new fields. * gas/testsuite/gas/arm/armv8-a-it-bad.d: New testcase. * gas/testsuite/gas/arm/armv8-a-it-bad.l: Likewise. * gas/testsuite/gas/arm/armv8-a-it-bad.s: Likewise. * gas/testsuite/gas/arm/ldr-t-bad.s: Update testcase. * gas/testsuite/gas/arm/ldr-t.d: Likewise. * gas/testsuite/gas/arm/ldr-t.s: Likewise. * gas/testsuite/gas/arm/neon-cond-bad-inc.s: Likewise. * gas/testsuite/gas/arm/sp-pc-validations-bad-t: Likewise. * gas/testsuite/gas/arm/vfp-fma-inc.s: Likewise. * gas/testsuite/gas/arm/vfp-neon-syntax-inc.s: Likewise.
This commit is contained in:
Matthew Gretton-Dann
@ -1,3 +1,14 @@
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (do_t_it): Fully initialise now_it.
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(new_automatic_it_block): Likewise.
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(handle_it_block): Record whether current instruction is
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conditionally executed.
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* config/tc-arm.c (depr_insn_mask): New structure.
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(depr_it_insns): New variable.
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(it_fsm_post_encode): Warn on deprecated uses.
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* config/tc-arm.h (current_it): Add new fields.
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (deprecated_coproc_regs_s): New structure.
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@ -10356,6 +10356,7 @@ do_t_it (void)
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set_it_insn_type (IT_INSN);
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now_it.mask = (inst.instruction & 0xf) | 0x10;
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now_it.cc = cond;
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now_it.warn_deprecated = FALSE;
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/* If the condition is a negative condition, invert the mask. */
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if ((cond & 0x1) == 0x0)
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@ -10363,13 +10364,25 @@ do_t_it (void)
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unsigned int mask = inst.instruction & 0x000f;
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if ((mask & 0x7) == 0)
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/* no conversion needed */;
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{
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/* No conversion needed. */
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now_it.block_length = 1;
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}
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else if ((mask & 0x3) == 0)
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mask ^= 0x8;
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{
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mask ^= 0x8;
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now_it.block_length = 2;
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}
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else if ((mask & 0x1) == 0)
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mask ^= 0xC;
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{
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mask ^= 0xC;
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now_it.block_length = 3;
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}
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else
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mask ^= 0xE;
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{
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mask ^= 0xE;
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now_it.block_length = 4;
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}
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inst.instruction &= 0xfff0;
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inst.instruction |= mask;
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@ -16187,6 +16200,8 @@ new_automatic_it_block (int cond)
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now_it.block_length = 1;
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mapping_state (MAP_THUMB);
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now_it.insn = output_it_inst (cond, now_it.mask, NULL);
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now_it.warn_deprecated = FALSE;
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now_it.insn_cond = TRUE;
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}
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/* Close an automatic IT block.
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@ -16294,6 +16309,7 @@ static int
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handle_it_state (void)
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{
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now_it.state_handled = 1;
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now_it.insn_cond = FALSE;
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switch (now_it.state)
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{
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@ -16371,6 +16387,7 @@ handle_it_state (void)
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}
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else
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{
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now_it.insn_cond = TRUE;
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now_it_add_mask (inst.cond);
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}
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@ -16382,6 +16399,7 @@ handle_it_state (void)
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case NEUTRAL_IT_INSN:
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now_it.block_length++;
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now_it.insn_cond = TRUE;
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if (now_it.block_length > 4)
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force_automatic_it_block_close ();
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@ -16404,6 +16422,7 @@ handle_it_state (void)
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now_it.mask <<= 1;
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now_it.mask &= 0x1f;
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is_last = (now_it.mask == 0x10);
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now_it.insn_cond = TRUE;
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switch (inst.it_insn_type)
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{
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@ -16448,6 +16467,25 @@ handle_it_state (void)
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return SUCCESS;
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}
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struct depr_insn_mask
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{
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unsigned long pattern;
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unsigned long mask;
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const char* description;
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};
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/* List of 16-bit instruction patterns deprecated in an IT block in
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ARMv8. */
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static const struct depr_insn_mask depr_it_insns[] = {
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{ 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
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{ 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
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{ 0xa000, 0xb800, N_("ADR") },
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{ 0x4800, 0xf800, N_("Literal loads") },
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{ 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
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{ 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
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{ 0, 0, NULL }
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};
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static void
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it_fsm_post_encode (void)
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{
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@ -16456,6 +16494,44 @@ it_fsm_post_encode (void)
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if (!now_it.state_handled)
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handle_it_state ();
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if (now_it.insn_cond
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&& !now_it.warn_deprecated
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&& warn_on_deprecated
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&& ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
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{
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if (inst.instruction >= 0x10000)
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{
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as_warn (_("it blocks containing wide Thumb instructions are "
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"deprecated in ARMv8"));
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now_it.warn_deprecated = TRUE;
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}
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else
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{
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const struct depr_insn_mask *p = depr_it_insns;
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while (p->mask != 0)
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{
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if ((inst.instruction & p->mask) == p->pattern)
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{
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as_warn (_("it blocks containing 16-bit Thumb intsructions "
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"of the following class are deprecated in ARMv8: "
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"%s"), p->description);
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now_it.warn_deprecated = TRUE;
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break;
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}
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++p;
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}
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}
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if (now_it.block_length > 1)
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{
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as_warn (_("it blocks of more than one conditional instruction are "
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"deprecated in ARMv8"));
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now_it.warn_deprecated = TRUE;
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}
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}
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is_last = (now_it.mask == 0x10);
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if (is_last)
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{
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@ -257,6 +257,8 @@ struct current_it
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int block_length;
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char *insn;
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int state_handled;
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int warn_deprecated;
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int insn_cond;
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};
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#ifdef OBJ_ELF
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@ -1,3 +1,16 @@
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/armv8-a-it-bad.d: New testcase.
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* gas/arm/armv8-a-it-bad.l: Likewise.
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* gas/arm/armv8-a-it-bad.s: Likewise.
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* gas/arm/ldr-t-bad.s: Update testcase.
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* gas/arm/ldr-t.d: Likewise.
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* gas/arm/ldr-t.s: Likewise.
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* gas/arm/neon-cond-bad-inc.s: Likewise.
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* gas/arm/sp-pc-validations-bad-t: Likewise.
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* gas/arm/vfp-fma-inc.s: Likewise.
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* gas/arm/vfp-neon-syntax-inc.s: Likewise.
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/armv8-a-bad.l: Update testcase.
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3
gas/testsuite/gas/arm/armv8-a-it-bad.d
Normal file
3
gas/testsuite/gas/arm/armv8-a-it-bad.d
Normal file
@ -0,0 +1,3 @@
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#name: Deprecated IT blocks (ARM v8)
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#error-output: armv8-a-it-bad.l
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#as: -mimplicit-it=always
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14
gas/testsuite/gas/arm/armv8-a-it-bad.l
Normal file
14
gas/testsuite/gas/arm/armv8-a-it-bad.l
Normal file
@ -0,0 +1,14 @@
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.*: Assembler messages:
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.*:7: Warning: it blocks containing wide Thumb instructions are deprecated in ARMv8
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.*:15: Warning: it blocks of more than one conditional instruction are deprecated in ARMv8
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.*:20: Warning: it blocks of more than one conditional instruction are deprecated in ARMv8
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.*:30: Warning: it blocks containing wide Thumb instructions are deprecated in ARMv8
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.*:36: Warning: it blocks of more than one conditional instruction are deprecated in ARMv8
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.*:40: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
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.*:43: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions
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.*:49: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Literal loads
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.*:52: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Hi-register ADD, MOV, CMP, BX, BLX using pc
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.*:55: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
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.*:55: Error: r15 not allowed here -- `addeq r0,pc,pc'
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.*:58: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
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.*:58: Error: r15 not allowed here -- `addeq pc,r0,r0'
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58
gas/testsuite/gas/arm/armv8-a-it-bad.s
Normal file
58
gas/testsuite/gas/arm/armv8-a-it-bad.s
Normal file
@ -0,0 +1,58 @@
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.syntax unified
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.arch armv8-a
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.thumb
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@ Wide instruction in IT block is deprecated.
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it eq
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ldrdeq r0, [r1]
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@ This IT block is not deprecated.
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it eq
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moveq r2, r3
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@ IT block of more than one instruction is deprecated.
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itt eq
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moveq r0, r1
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moveq r2, r3
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@ Even for auto IT blocks
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moveq r2, r3
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movne r2, r3
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adds r0, r1
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@ This automatic IT block is valid
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moveq r2,r3
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add r0, r1, r2
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@ This one is too wide.
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ldrdeq r0, [r1]
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add r0, r1, r2
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@ Test automatic IT block generation at end of a file.
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movne r0, r1
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moveq r1, r0
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@ Test the various classes of 16-bit instructions that are deprecated.
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it eq
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svceq 0
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it eq
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uxtheq r0, r1
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it eq
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addeq r0, pc, #0
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it eq
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ldreq r0, [pc, #4]
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it eq
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bxeq pc
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it eq
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addeq r0, pc, pc
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it eq
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addeq pc, r0, r0
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@ -1,5 +1,5 @@
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.syntax unified
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.arch armv7-a
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.thumb
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@ldr-immediate
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@ -11,22 +11,22 @@ Disassembly of section [^>]+:
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0+10 <[^>]+> f8df f004 ldr.w pc, \[pc, #4\] ; 0+18 <[^>]+0x18>
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0+14 <[^>]+> bfa2 ittt ge
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0+16 <[^>]+> 4901 ldrge r1, \[pc, #4\] ; \(0+1c <[^>]+0x1c>\)
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0+18 <[^>]+> 46c0 nopge ; \(mov r8, r8\)
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0+1a <[^>]+> 46c0 nopge ; \(mov r8, r8\)
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0+18 <[^>]+> bf00 nopge
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0+1a <[^>]+> bf00 nopge
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0+1c <[^>]+> bfa8 it ge
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0+1e <[^>]+> f8df f004 ldrge.w pc, \[pc, #4\] ; 0+24 <[^>]+0x24>
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0+22 <[^>]+> bfa2 ittt ge
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0+24 <[^>]+> f85f 1ab8 ldrge.w r1, \[pc, #-2744\] ; fffff570 <[^>]+>
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0+28 <[^>]+> 46c0 nopge ; \(mov r8, r8\)
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0+2a <[^>]+> 46c0 nopge ; \(mov r8, r8\)
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0+28 <[^>]+> bf00 nopge
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0+2a <[^>]+> bf00 nopge
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0+2c <[^>]+> bfa8 it ge
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0+2e <[^>]+> f85f fab6 ldrge.w pc, \[pc, #-2742\] ; fffff57a <[^>]+>
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0+32 <[^>]+> f85f 1ab9 ldr.w r1, \[pc, #-2745\] ; fffff57b <[^>]+>
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0+36 <[^>]+> f85f fab6 ldr.w pc, \[pc, #-2742\] ; fffff582 <[^>]+>
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0+3a <[^>]+> bfa2 ittt ge
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0+3c <[^>]+> 5851 ldrge r1, \[r2, r1\]
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0+3e <[^>]+> 46c0 nopge ; \(mov r8, r8\)
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0+40 <[^>]+> 46c0 nopge ; \(mov r8, r8\)
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0+3e <[^>]+> bf00 nopge
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0+40 <[^>]+> bf00 nopge
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0+42 <[^>]+> bfa8 it ge
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0+44 <[^>]+> f852 f001 ldrge.w pc, \[r2, r1\]
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0+48 <[^>]+> 58d1 ldr r1, \[r2, r3\]
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@ -1,5 +1,5 @@
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.syntax unified
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.arch armv7-a
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.thumb
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.global foo
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foo:
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@ -1,9 +1,9 @@
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# Check for illegal conditional Neon instructions in ARM mode. The instructions
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# which overlap with VFP are the tricky cases, so test those.
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.include "itblock.s"
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.syntax unified
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.arch armv7-a
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.fpu neon
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.text
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func:
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itblock 4 eq
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@ -1,6 +1,6 @@
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.syntax unified
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.arch armv7-a
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.thumb
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.macro it_test opcode operands:vararg
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itt eq
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\opcode\()eq r15, \operands
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@ -1,4 +1,6 @@
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.syntax unified
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.arch armv7-a
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.fpu neon-vfpv4
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.include "itblock.s"
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@ -1,5 +1,6 @@
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@ VFP with Neon-style syntax
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.syntax unified
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.arch armv7-a
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.include "itblock.s"
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Block a user