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https://github.com/espressif/binutils-gdb.git
synced 2025-07-02 02:45:37 +08:00
x86: drop dqa_mode
I assume this mode was needed when EVEX.W handling wasn't really correct yet for other than 64-bit mode. It's clearly not needed anymore. Its elimination also allows dropping the EVEX.W split of VCVT{,U}SI2SS. (For the record, the dropped mode would have been wrong if used in any table entry not already guaranteeing EVEX.W=1.)
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@ -1,3 +1,14 @@
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2019-06-25 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
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Delete.
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(intel_operand_size, OP_E_register, OP_E_memory): Drop handling
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of dqa_mode.
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* i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
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entries here.
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* i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
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entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
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2019-06-25 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
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@ -64,7 +64,7 @@
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/* PREFIX_EVEX_0F2A */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F2A_P_1) },
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{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F2A_P_3) },
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},
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@ -404,7 +404,7 @@
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/* PREFIX_EVEX_0F7B */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F7B_P_1) },
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{ "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F7B_P_2) },
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{ VEX_W_TABLE (EVEX_W_0F7B_P_3) },
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},
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@ -145,15 +145,10 @@
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{ Bad_Opcode },
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{ "vmovapd", { EXxS, XM }, 0 },
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},
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/* EVEX_W_0F2A_P_1 */
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{
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{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 },
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{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 },
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},
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/* EVEX_W_0F2A_P_3 */
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{
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{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 },
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{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edqa }, 0 },
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{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
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},
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/* EVEX_W_0F2B_P_0 */
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{
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@ -477,11 +472,6 @@
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{ "vcvtudq2ps", { XM, EXx, EXxEVexR }, 0 },
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{ "vcvtuqq2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
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},
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/* EVEX_W_0F7B_P_1 */
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{
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{ "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 },
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{ "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 },
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},
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/* EVEX_W_0F7B_P_2 */
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{
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{ "vcvtps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 },
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@ -490,7 +480,7 @@
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/* EVEX_W_0F7B_P_3 */
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{
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{ "vcvtusi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 },
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{ "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edqa }, 0 },
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{ "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
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},
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/* EVEX_W_0F7E_P_1 */
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{
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@ -259,7 +259,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define Edb { OP_E, db_mode }
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#define Edw { OP_E, dw_mode }
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#define Edqd { OP_E, dqd_mode }
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#define Edqa { OP_E, dqa_mode }
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#define Eq { OP_E, q_mode }
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#define indirEv { OP_indirE, indir_v_mode }
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#define indirEp { OP_indirE, f_mode }
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@ -591,8 +590,6 @@ enum
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dw_mode,
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/* registers like dq_mode, memory like d_mode. */
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dqd_mode,
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/* operand size depends on the W bit as well as address mode. */
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dqa_mode,
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/* normal vex mode */
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vex_mode,
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/* 128bit vex mode */
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@ -2076,7 +2073,6 @@ enum
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EVEX_W_0F28_P_2,
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EVEX_W_0F29_P_0,
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EVEX_W_0F29_P_2,
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EVEX_W_0F2A_P_1,
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EVEX_W_0F2A_P_3,
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EVEX_W_0F2B_P_0,
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EVEX_W_0F2B_P_2,
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@ -2149,7 +2145,6 @@ enum
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EVEX_W_0F7A_P_1,
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EVEX_W_0F7A_P_2,
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EVEX_W_0F7A_P_3,
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EVEX_W_0F7B_P_1,
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EVEX_W_0F7B_P_2,
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EVEX_W_0F7B_P_3,
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EVEX_W_0F7E_P_1,
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@ -13522,7 +13517,6 @@ intel_operand_size (int bytemode, int sizeflag)
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case q_swap_mode:
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oappend ("QWORD PTR ");
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break;
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case dqa_mode:
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case m_mode:
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if (address_mode == mode_64bit)
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oappend ("QWORD PTR ");
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@ -13881,7 +13875,6 @@ OP_E_register (int bytemode, int sizeflag)
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case dqb_mode:
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case dqd_mode:
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case dqw_mode:
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case dqa_mode:
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USED_REX (REX_W);
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if (rex & REX_W)
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names = names64;
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@ -14031,9 +14024,6 @@ OP_E_memory (int bytemode, int sizeflag)
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case xmm_mb_mode:
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shift = 0;
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break;
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case dqa_mode:
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shift = address_mode == mode_64bit ? 3 : 2;
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break;
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default:
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abort ();
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}
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