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* sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.

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David Edelsohn
1996-03-31 21:32:00 +00:00
parent 323b430fc4
commit 4be1b31325
2 changed files with 18 additions and 4 deletions
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8
include/opcode/ChangeLog
View File

@ -1,3 +1,11 @@
Sun Mar 31 13:30:03 1996 Doug Evans <dje@canuck.cygnus.com>
* sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.
Thu Mar 7 15:08:23 1996 Doug Evans <dje@charmed.cygnus.com>
* sparc.h (O): Mark operand letter as in use.
Tue Feb 20 20:46:21 1996 Doug Evans <dje@charmed.cygnus.com>
* sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare.

14
include/opcode/sparc.h
View File

@ -49,13 +49,18 @@ enum sparc_opcode_arch_val {
/* The highest architecture in the table. */
#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
insn encoding/decoding. */
#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
/* Table of cpu variants. */
struct sparc_opcode_arch {
const char *name;
/* Mask of sparc_opcode_arch_val's supported.
EG: For v7 this would be ((1 << v6) | (1 << v7)). */
/* These are short's because sparc_opcode.architecture is. */
EG: For v7 this would be
(SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
These are short's because sparc_opcode.architecture is. */
short supported;
};
@ -144,7 +149,8 @@ Kinds of operands:
z %icc. (v9)
Z %xcc. (v9)
q Floating point queue.
r Single register that is both rs1 and rsd.
r Single register that is both rs1 and rd.
O Single register that is both rs2 and rd.
Q Coprocessor queue.
S Special case.
t Trap base register.
@ -167,7 +173,7 @@ Kinds of operands:
x OPF field (v9 impdep).
The following chars are unused: (note: ,[] are used as punctuation)
[OXY3450]
[XY3450]
*/