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[PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb]
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vshrnt, M_MNEM_vshrnb, M_MNEM_vrshrnt, M_MNEM_vqshrnt, M_MNEM_vqshrnb, M_MNEM_vqshrunt, M_MNEM_vqshrunb, M_MNEM_vrshrnb, M_MNEM_vqrshrnt, M_MNEM_vqrshrnb, M_MNEM_vqrshrunt, M_MNEM_vqrshrunb): New instruction encodings. (do_mve_vshrn): New encoding function. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vqrshrn-bad.d: New test. * testsuite/gas/arm/mve-vqrshrn-bad.l: New test. * testsuite/gas/arm/mve-vqrshrn-bad.s: New test. * testsuite/gas/arm/mve-vshrn-bad.d: New test. * testsuite/gas/arm/mve-vshrn-bad.l: New test. * testsuite/gas/arm/mve-vshrn-bad.s: New test.
This commit is contained in:
Andre Vieira
@ -1,3 +1,18 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (M_MNEM_vshrnt, M_MNEM_vshrnb, M_MNEM_vrshrnt,
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M_MNEM_vqshrnt, M_MNEM_vqshrnb, M_MNEM_vqshrunt, M_MNEM_vqshrunb,
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M_MNEM_vrshrnb, M_MNEM_vqrshrnt, M_MNEM_vqrshrnb, M_MNEM_vqrshrunt,
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M_MNEM_vqrshrunb): New instruction encodings.
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(do_mve_vshrn): New encoding function.
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(insns): Add entries for MVE mnemonics.
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* testsuite/gas/arm/mve-vqrshrn-bad.d: New test.
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* testsuite/gas/arm/mve-vqrshrn-bad.l: New test.
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* testsuite/gas/arm/mve-vqrshrn-bad.s: New test.
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* testsuite/gas/arm/mve-vshrn-bad.d: New test.
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* testsuite/gas/arm/mve-vshrn-bad.l: New test.
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* testsuite/gas/arm/mve-vshrn-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (M_MNEM_vqmovnt, M_MNEM_vqmovnb,
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@ -14206,6 +14206,18 @@ do_t_loloop (void)
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#define M_MNEM_vqmovnb 0xee330e01
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#define M_MNEM_vqmovunt 0xee311e81
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#define M_MNEM_vqmovunb 0xee310e81
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#define M_MNEM_vshrnt 0xee801fc1
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#define M_MNEM_vshrnb 0xee800fc1
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#define M_MNEM_vrshrnt 0xfe801fc1
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#define M_MNEM_vqshrnt 0xee801f40
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#define M_MNEM_vqshrnb 0xee800f40
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#define M_MNEM_vqshrunt 0xee801fc0
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#define M_MNEM_vqshrunb 0xee800fc0
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#define M_MNEM_vrshrnb 0xfe800fc1
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#define M_MNEM_vqrshrnt 0xee801f41
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#define M_MNEM_vqrshrnb 0xee800f41
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#define M_MNEM_vqrshrunt 0xfe801fc0
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#define M_MNEM_vqrshrunb 0xfe800fc0
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/* Neon instruction encoder helpers. */
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@ -15750,6 +15762,58 @@ do_mve_vmlas (void)
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inst.is_neon = 1;
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}
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static void
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do_mve_vshrn (void)
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{
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unsigned types;
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switch (inst.instruction)
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{
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case M_MNEM_vshrnt:
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case M_MNEM_vshrnb:
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case M_MNEM_vrshrnt:
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case M_MNEM_vrshrnb:
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types = N_I16 | N_I32;
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break;
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case M_MNEM_vqshrnt:
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case M_MNEM_vqshrnb:
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case M_MNEM_vqrshrnt:
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case M_MNEM_vqrshrnb:
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types = N_U16 | N_U32 | N_S16 | N_S32;
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break;
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case M_MNEM_vqshrunt:
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case M_MNEM_vqshrunb:
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case M_MNEM_vqrshrunt:
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case M_MNEM_vqrshrunb:
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types = N_S16 | N_S32;
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break;
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default:
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abort ();
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}
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struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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unsigned Qd = inst.operands[0].reg;
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unsigned Qm = inst.operands[1].reg;
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unsigned imm = inst.operands[2].imm;
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constraint (imm < 1 || ((unsigned) imm) > (et.size / 2),
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et.size == 16
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? _("immediate operand expected in the range [1,8]")
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: _("immediate operand expected in the range [1,16]"));
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inst.instruction |= (et.type == NT_unsigned) << 28;
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inst.instruction |= HI1 (Qd) << 22;
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inst.instruction |= (et.size - imm) << 16;
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inst.instruction |= LOW4 (Qd) << 12;
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inst.instruction |= HI1 (Qm) << 5;
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inst.instruction |= LOW4 (Qm);
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inst.is_neon = 1;
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}
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static void
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do_mve_vqmovn (void)
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{
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@ -24946,6 +25010,19 @@ static const struct asm_opcode insns[] =
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mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn),
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mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn),
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mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
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mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
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5
gas/testsuite/gas/arm/mve-vqrshrn-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vqrshrn-bad.d
Normal file
@ -0,0 +1,5 @@
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#name: bad MVE VQRSHRNT, VQRSHRNB, VQRHSRUNT and MVQRSHRUNB instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vqrshrn-bad.l
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.*: +file format .*arm.*
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71
gas/testsuite/gas/arm/mve-vqrshrn-bad.l
Normal file
71
gas/testsuite/gas/arm/mve-vqrshrn-bad.l
Normal file
@ -0,0 +1,71 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vqrshrnt.s8 q0,q1,#1'
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[^:]*:11: Error: bad type in SIMD instruction -- `vqrshrnt.s64 q0,q1,#1'
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[^:]*:12: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnt.s16 q0,q1,#0'
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[^:]*:13: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnt.s16 q0,q1,#9'
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[^:]*:14: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnt.s32 q0,q1,#0'
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[^:]*:15: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnt.s32 q0,q1,#17'
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[^:]*:16: Error: bad type in SIMD instruction -- `vqrshrnb.s8 q0,q1,#1'
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[^:]*:17: Error: bad type in SIMD instruction -- `vqrshrnb.s64 q0,q1,#1'
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[^:]*:18: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnb.s16 q0,q1,#0'
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[^:]*:19: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnb.s16 q0,q1,#9'
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[^:]*:20: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnb.s32 q0,q1,#0'
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[^:]*:21: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnb.s32 q0,q1,#17'
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[^:]*:22: Error: bad type in SIMD instruction -- `vqrshrunt.s8 q0,q1,#1'
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[^:]*:23: Error: bad type in SIMD instruction -- `vqrshrunt.s64 q0,q1,#1'
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[^:]*:24: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunt.s16 q0,q1,#0'
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[^:]*:25: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunt.s16 q0,q1,#9'
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[^:]*:26: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunt.s32 q0,q1,#0'
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[^:]*:27: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunt.s32 q0,q1,#17'
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[^:]*:28: Error: bad type in SIMD instruction -- `vqrshrunt.u16 q0,q1,#1'
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[^:]*:29: Error: bad type in SIMD instruction -- `vqrshrunb.s8 q0,q1,#1'
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[^:]*:30: Error: bad type in SIMD instruction -- `vqrshrunb.s64 q0,q1,#1'
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[^:]*:31: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunb.s16 q0,q1,#0'
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[^:]*:32: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunb.s16 q0,q1,#9'
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[^:]*:33: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunb.s32 q0,q1,#0'
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[^:]*:34: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunb.s32 q0,q1,#17'
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[^:]*:35: Error: bad type in SIMD instruction -- `vqrshrunb.u16 q0,q1,#1'
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:41: Error: syntax error -- `vqrshrnteq.s16 q0,q1,#1'
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[^:]*:42: Error: syntax error -- `vqrshrnteq.s16 q0,q1,#1'
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[^:]*:44: Error: syntax error -- `vqrshrnteq.s16 q0,q1,#1'
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[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshrntt.s16 q0,q1,#1'
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[^:]*:47: Error: instruction missing MVE vector predication code -- `vqrshrnt.s16 q0,q1,#1'
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[^:]*:49: Error: syntax error -- `vqrshrnbeq.s16 q0,q1,#1'
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[^:]*:50: Error: syntax error -- `vqrshrnbeq.s16 q0,q1,#1'
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[^:]*:52: Error: syntax error -- `vqrshrnbeq.s16 q0,q1,#1'
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[^:]*:53: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshrnbt.s16 q0,q1,#1'
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[^:]*:55: Error: instruction missing MVE vector predication code -- `vqrshrnb.s16 q0,q1,#1'
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[^:]*:57: Error: syntax error -- `vqrshrunteq.s16 q0,q1,#1'
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[^:]*:58: Error: syntax error -- `vqrshrunteq.s16 q0,q1,#1'
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[^:]*:60: Error: syntax error -- `vqrshrunteq.s16 q0,q1,#1'
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[^:]*:61: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshruntt.s16 q0,q1,#1'
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[^:]*:63: Error: instruction missing MVE vector predication code -- `vqrshrunt.s16 q0,q1,#1'
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[^:]*:65: Error: syntax error -- `vqrshrunbeq.s16 q0,q1,#1'
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[^:]*:66: Error: syntax error -- `vqrshrunbeq.s16 q0,q1,#1'
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[^:]*:68: Error: syntax error -- `vqrshrunbeq.s16 q0,q1,#1'
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[^:]*:69: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshrunbt.s16 q0,q1,#1'
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[^:]*:71: Error: instruction missing MVE vector predication code -- `vqrshrunb.s16 q0,q1,#1'
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71
gas/testsuite/gas/arm/mve-vqrshrn-bad.s
Normal file
71
gas/testsuite/gas/arm/mve-vqrshrn-bad.s
Normal file
@ -0,0 +1,71 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s16 q0, q0, #1
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.endr
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.endm
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.syntax unified
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.thumb
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vqrshrnt.s8 q0, q1, #1
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vqrshrnt.s64 q0, q1, #1
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vqrshrnt.s16 q0, q1, #0
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vqrshrnt.s16 q0, q1, #9
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vqrshrnt.s32 q0, q1, #0
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vqrshrnt.s32 q0, q1, #17
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vqrshrnb.s8 q0, q1, #1
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vqrshrnb.s64 q0, q1, #1
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vqrshrnb.s16 q0, q1, #0
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vqrshrnb.s16 q0, q1, #9
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vqrshrnb.s32 q0, q1, #0
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vqrshrnb.s32 q0, q1, #17
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vqrshrunt.s8 q0, q1, #1
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vqrshrunt.s64 q0, q1, #1
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vqrshrunt.s16 q0, q1, #0
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vqrshrunt.s16 q0, q1, #9
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vqrshrunt.s32 q0, q1, #0
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vqrshrunt.s32 q0, q1, #17
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vqrshrunt.u16 q0, q1, #1
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vqrshrunb.s8 q0, q1, #1
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vqrshrunb.s64 q0, q1, #1
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vqrshrunb.s16 q0, q1, #0
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vqrshrunb.s16 q0, q1, #9
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vqrshrunb.s32 q0, q1, #0
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vqrshrunb.s32 q0, q1, #17
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vqrshrunb.u16 q0, q1, #1
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cond vqrshrnt
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cond vqrshrnb
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cond vqrshrunt
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cond vqrshrunb
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it eq
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vqrshrnteq.s16 q0, q1, #1
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vqrshrnteq.s16 q0, q1, #1
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vpst
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vqrshrnteq.s16 q0, q1, #1
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vqrshrntt.s16 q0, q1, #1
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vpst
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vqrshrnt.s16 q0, q1, #1
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it eq
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vqrshrnbeq.s16 q0, q1, #1
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vqrshrnbeq.s16 q0, q1, #1
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vpst
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vqrshrnbeq.s16 q0, q1, #1
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vqrshrnbt.s16 q0, q1, #1
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vpst
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vqrshrnb.s16 q0, q1, #1
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it eq
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vqrshrunteq.s16 q0, q1, #1
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vqrshrunteq.s16 q0, q1, #1
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vpst
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vqrshrunteq.s16 q0, q1, #1
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vqrshruntt.s16 q0, q1, #1
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vpst
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vqrshrunt.s16 q0, q1, #1
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it eq
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vqrshrunbeq.s16 q0, q1, #1
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vqrshrunbeq.s16 q0, q1, #1
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vpst
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vqrshrunbeq.s16 q0, q1, #1
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vqrshrunbt.s16 q0, q1, #1
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vpst
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vqrshrunb.s16 q0, q1, #1
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5
gas/testsuite/gas/arm/mve-vshrn-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vshrn-bad.d
Normal file
@ -0,0 +1,5 @@
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#name: bad MVE VSHRN and VRSHRN instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vshrn-bad.l
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.*: +file format .*arm.*
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57
gas/testsuite/gas/arm/mve-vshrn-bad.l
Normal file
57
gas/testsuite/gas/arm/mve-vshrn-bad.l
Normal file
@ -0,0 +1,57 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vshrnt.i64 q0,q1,#1'
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[^:]*:11: Error: bad type in SIMD instruction -- `vshrnb.i64 q0,q1,#1'
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[^:]*:12: Error: bad type in SIMD instruction -- `vrshrnt.i64 q0,q1,#1'
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[^:]*:13: Error: bad type in SIMD instruction -- `vrshrnb.i64 q0,q1,#1'
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[^:]*:14: Error: immediate operand expected in the range \[1,8\] -- `vshrnt.i16 q0,q1,#0'
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[^:]*:15: Error: immediate operand expected in the range \[1,8\] -- `vshrnt.i16 q0,q1,#9'
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[^:]*:16: Error: immediate operand expected in the range \[1,16\] -- `vshrnt.i32 q0,q1,#0'
|
||||
[^:]*:17: Error: immediate operand expected in the range \[1,16\] -- `vshrnt.i32 q0,q1,#17'
|
||||
[^:]*:18: Error: immediate operand expected in the range \[1,8\] -- `vshrnb.i16 q0,q1,#0'
|
||||
[^:]*:19: Error: immediate operand expected in the range \[1,8\] -- `vshrnb.i16 q0,q1,#9'
|
||||
[^:]*:20: Error: immediate operand expected in the range \[1,16\] -- `vshrnb.i32 q0,q1,#0'
|
||||
[^:]*:21: Error: immediate operand expected in the range \[1,16\] -- `vshrnb.i32 q0,q1,#17'
|
||||
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Error: syntax error -- `vshrnteq.i32 q0,q1,#1'
|
||||
[^:]*:28: Error: syntax error -- `vshrnteq.i32 q0,q1,#1'
|
||||
[^:]*:30: Error: syntax error -- `vshrnteq.i32 q0,q1,#1'
|
||||
[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vshrntt.i32 q0,q1,#1'
|
||||
[^:]*:33: Error: instruction missing MVE vector predication code -- `vshrnt.i32 q0,q1,#1'
|
||||
[^:]*:35: Error: syntax error -- `vshrnbeq.i32 q0,q1,#1'
|
||||
[^:]*:36: Error: syntax error -- `vshrnbeq.i32 q0,q1,#1'
|
||||
[^:]*:38: Error: syntax error -- `vshrnbeq.i32 q0,q1,#1'
|
||||
[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vshrnbt.i32 q0,q1,#1'
|
||||
[^:]*:41: Error: instruction missing MVE vector predication code -- `vshrnb.i32 q0,q1,#1'
|
||||
[^:]*:43: Error: syntax error -- `vrshrnteq.i32 q0,q1,#1'
|
||||
[^:]*:44: Error: syntax error -- `vrshrnteq.i32 q0,q1,#1'
|
||||
[^:]*:46: Error: syntax error -- `vrshrnteq.i32 q0,q1,#1'
|
||||
[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vrshrntt.i32 q0,q1,#1'
|
||||
[^:]*:49: Error: instruction missing MVE vector predication code -- `vrshrnt.i32 q0,q1,#1'
|
||||
[^:]*:51: Error: syntax error -- `vrshrnbeq.i32 q0,q1,#1'
|
||||
[^:]*:52: Error: syntax error -- `vrshrnbeq.i32 q0,q1,#1'
|
||||
[^:]*:54: Error: syntax error -- `vrshrnbeq.i32 q0,q1,#1'
|
||||
[^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vrshrnbt.i32 q0,q1,#1'
|
||||
[^:]*:57: Error: instruction missing MVE vector predication code -- `vrshrnb.i32 q0,q1,#1'
|
||||
57
gas/testsuite/gas/arm/mve-vshrn-bad.s
Normal file
57
gas/testsuite/gas/arm/mve-vshrn-bad.s
Normal file
@ -0,0 +1,57 @@
|
||||
.macro cond op
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().i32 q0, q1, #1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vshrnt.i64 q0, q1, #1
|
||||
vshrnb.i64 q0, q1, #1
|
||||
vrshrnt.i64 q0, q1, #1
|
||||
vrshrnb.i64 q0, q1, #1
|
||||
vshrnt.i16 q0, q1, #0
|
||||
vshrnt.i16 q0, q1, #9
|
||||
vshrnt.i32 q0, q1, #0
|
||||
vshrnt.i32 q0, q1, #17
|
||||
vshrnb.i16 q0, q1, #0
|
||||
vshrnb.i16 q0, q1, #9
|
||||
vshrnb.i32 q0, q1, #0
|
||||
vshrnb.i32 q0, q1, #17
|
||||
cond vshrnt
|
||||
cond vshrnb
|
||||
cond vrshrnt
|
||||
cond vrshrnb
|
||||
it eq
|
||||
vshrnteq.i32 q0, q1, #1
|
||||
vshrnteq.i32 q0, q1, #1
|
||||
vpst
|
||||
vshrnteq.i32 q0, q1, #1
|
||||
vshrntt.i32 q0, q1, #1
|
||||
vpst
|
||||
vshrnt.i32 q0, q1, #1
|
||||
it eq
|
||||
vshrnbeq.i32 q0, q1, #1
|
||||
vshrnbeq.i32 q0, q1, #1
|
||||
vpst
|
||||
vshrnbeq.i32 q0, q1, #1
|
||||
vshrnbt.i32 q0, q1, #1
|
||||
vpst
|
||||
vshrnb.i32 q0, q1, #1
|
||||
it eq
|
||||
vrshrnteq.i32 q0, q1, #1
|
||||
vrshrnteq.i32 q0, q1, #1
|
||||
vpst
|
||||
vrshrnteq.i32 q0, q1, #1
|
||||
vrshrntt.i32 q0, q1, #1
|
||||
vpst
|
||||
vrshrnt.i32 q0, q1, #1
|
||||
it eq
|
||||
vrshrnbeq.i32 q0, q1, #1
|
||||
vrshrnbeq.i32 q0, q1, #1
|
||||
vpst
|
||||
vrshrnbeq.i32 q0, q1, #1
|
||||
vrshrnbt.i32 q0, q1, #1
|
||||
vpst
|
||||
vrshrnb.i32 q0, q1, #1
|
||||
Reference in New Issue
Block a user