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https://github.com/espressif/binutils-gdb.git
synced 2025-06-24 12:23:31 +08:00
x86: honor absolute section when emitting code
Various provisions exist for insns to be placed in the absolute section, yet actually trying to do so didn't work. While data emission (of non- zero values) is not allowed by generic code, I think this functionality is useful for the programmer to be able to determine the size of insns. Therefore, rather than turning the silnet failure into a verbose one, make things mostly work; the one class of insns not supported (yet) are branches (JMP and Jcc) with dynamically determined displacement widths. In this one case, an error now gets reported instead of silently ignoring the code. Also avoid recording ISA / feature usage for insns emitted to the absolute section.
This commit is contained in:
Jan Beulich
@ -1,3 +1,16 @@
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2020-07-20 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (frag_opcode_byte): New.
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(output_branch): Emit error when in absolute section.
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(output_jump, output_insn): Use frag_opcode_byte. Handle being
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in absolute section.
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(output_interseg_jump, output_disp, output_imm): Handle being in
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absolute section.
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* testsuite/gas/i386/sizing.s,
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testsuite/gas/i386/sizing32.d,
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testsuite/gas/i386/sizing64.d: New.
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* testsuite/gas/i386/i386.exp: Run new tests.
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2020-07-20 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/i386.exp: Include *-*-vxworks alongside
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@ -8426,6 +8426,15 @@ build_modrm_byte (void)
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return default_seg;
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}
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static INLINE void
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frag_opcode_byte (unsigned char byte)
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{
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if (now_seg != absolute_section)
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FRAG_APPEND_1_CHAR (byte);
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else
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++abs_section_offset;
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}
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static unsigned int
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flip_code16 (unsigned int code16)
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{
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@ -8449,6 +8458,12 @@ output_branch (void)
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symbolS *sym;
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offsetT off;
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if (now_seg == absolute_section)
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{
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as_bad (_("relaxable branches not supported in absolute section"));
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return;
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}
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code16 = flag_code == CODE_16BIT ? CODE16 : 0;
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size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
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@ -8578,14 +8593,14 @@ output_jump (void)
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size = 1;
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if (i.prefix[ADDR_PREFIX] != 0)
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{
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FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
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frag_opcode_byte (ADDR_PREFIX_OPCODE);
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i.prefixes -= 1;
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}
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/* Pentium4 branch hints. */
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if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
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|| i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
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{
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FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
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frag_opcode_byte (i.prefix[SEG_PREFIX]);
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i.prefixes--;
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}
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}
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@ -8599,7 +8614,7 @@ output_jump (void)
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if (i.prefix[DATA_PREFIX] != 0)
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{
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FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
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frag_opcode_byte (DATA_PREFIX_OPCODE);
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i.prefixes -= 1;
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code16 ^= flip_code16(code16);
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}
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@ -8612,19 +8627,25 @@ output_jump (void)
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/* BND prefixed jump. */
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if (i.prefix[BND_PREFIX] != 0)
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{
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FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
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frag_opcode_byte (i.prefix[BND_PREFIX]);
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i.prefixes -= 1;
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}
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if (i.prefix[REX_PREFIX] != 0)
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{
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FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
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frag_opcode_byte (i.prefix[REX_PREFIX]);
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i.prefixes -= 1;
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}
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if (i.prefixes != 0)
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as_warn (_("skipping prefixes on `%s'"), i.tm.name);
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if (now_seg == absolute_section)
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{
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abs_section_offset += i.tm.opcode_length + size;
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return;
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}
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p = frag_more (i.tm.opcode_length + size);
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switch (i.tm.opcode_length)
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{
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@ -8686,6 +8707,12 @@ output_interseg_jump (void)
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if (i.prefixes != 0)
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as_warn (_("skipping prefixes on `%s'"), i.tm.name);
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if (now_seg == absolute_section)
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{
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abs_section_offset += prefix + 1 + 2 + size;
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return;
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}
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/* 1 opcode; 2 segment; offset */
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p = frag_more (prefix + 1 + 2 + size);
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@ -9098,7 +9125,7 @@ output_insn (void)
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enum mf_jcc_kind mf_jcc = mf_jcc_jo;
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#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
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if (IS_ELF && x86_used_note)
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if (IS_ELF && x86_used_note && now_seg != absolute_section)
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{
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if (i.tm.cpu_flags.bitfield.cpucmov)
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x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV;
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@ -9237,14 +9264,20 @@ output_insn (void)
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&& (i.tm.base_opcode == 0xfaee8
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|| i.tm.base_opcode == 0xfaef0
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|| i.tm.base_opcode == 0xfaef8))
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{
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/* Encode lfence, mfence, and sfence as
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f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
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offsetT val = 0x240483f0ULL;
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p = frag_more (5);
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md_number_to_chars (p, val, 5);
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return;
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}
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{
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/* Encode lfence, mfence, and sfence as
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f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
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if (now_seg != absolute_section)
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{
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offsetT val = 0x240483f0ULL;
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p = frag_more (5);
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md_number_to_chars (p, val, 5);
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}
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else
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abs_section_offset += 5;
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return;
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}
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/* Some processors fail on LOCK prefix. This options makes
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assembler ignore LOCK prefix and serves as a workaround. */
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@ -9343,7 +9376,7 @@ output_insn (void)
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/* The prefix bytes. */
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for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
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if (*q)
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FRAG_APPEND_1_CHAR (*q);
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frag_opcode_byte (*q);
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}
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else
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{
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@ -9353,7 +9386,7 @@ output_insn (void)
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{
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case SEG_PREFIX:
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case ADDR_PREFIX:
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FRAG_APPEND_1_CHAR (*q);
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frag_opcode_byte (*q);
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break;
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default:
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/* There should be no other prefixes for instructions
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@ -9367,13 +9400,20 @@ output_insn (void)
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if (i.vrex)
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abort ();
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/* Now the VEX prefix. */
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p = frag_more (i.vex.length);
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for (j = 0; j < i.vex.length; j++)
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p[j] = i.vex.bytes[j];
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if (now_seg != absolute_section)
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{
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p = frag_more (i.vex.length);
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for (j = 0; j < i.vex.length; j++)
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p[j] = i.vex.bytes[j];
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}
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else
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abs_section_offset += i.vex.length;
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}
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/* Now the opcode; be careful about word order here! */
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if (i.tm.opcode_length == 1)
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if (now_seg == absolute_section)
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abs_section_offset += i.tm.opcode_length;
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else if (i.tm.opcode_length == 1)
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{
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FRAG_APPEND_1_CHAR (i.tm.base_opcode);
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}
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@ -9406,9 +9446,9 @@ output_insn (void)
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/* Now the modrm byte and sib byte (if present). */
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if (i.tm.opcode_modifier.modrm)
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{
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FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
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| i.rm.reg << 3
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| i.rm.mode << 6));
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frag_opcode_byte ((i.rm.regmem << 0)
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| (i.rm.reg << 3)
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| (i.rm.mode << 6));
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/* If i.rm.regmem == ESP (4)
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&& i.rm.mode != (Register mode)
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&& not 16 bit
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@ -9416,9 +9456,9 @@ output_insn (void)
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if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
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&& i.rm.mode != 3
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&& !(i.base_reg && i.base_reg->reg_type.bitfield.word))
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FRAG_APPEND_1_CHAR ((i.sib.base << 0
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| i.sib.index << 3
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| i.sib.scale << 6));
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frag_opcode_byte ((i.sib.base << 0)
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| (i.sib.index << 3)
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| (i.sib.scale << 6));
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}
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if (i.disp_operands)
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@ -9586,9 +9626,12 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off)
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{
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if (operand_type_check (i.types[n], disp))
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{
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if (i.op[n].disps->X_op == O_constant)
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int size = disp_size (n);
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if (now_seg == absolute_section)
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abs_section_offset += size;
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else if (i.op[n].disps->X_op == O_constant)
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{
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int size = disp_size (n);
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offsetT val = i.op[n].disps->X_add_number;
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val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
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@ -9599,7 +9642,6 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off)
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else
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{
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enum bfd_reloc_code_real reloc_type;
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int size = disp_size (n);
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int sign = i.types[n].bitfield.disp32s;
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int pcrel = (i.flags[n] & Operand_PCrel) != 0;
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fixS *fixP;
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@ -9732,9 +9774,12 @@ output_imm (fragS *insn_start_frag, offsetT insn_start_off)
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if (operand_type_check (i.types[n], imm))
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{
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if (i.op[n].imms->X_op == O_constant)
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int size = imm_size (n);
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if (now_seg == absolute_section)
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abs_section_offset += size;
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else if (i.op[n].imms->X_op == O_constant)
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{
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int size = imm_size (n);
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offsetT val;
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val = offset_in_range (i.op[n].imms->X_add_number,
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@ -9749,7 +9794,6 @@ output_imm (fragS *insn_start_frag, offsetT insn_start_off)
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non-absolute imms). Try to support other
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sizes ... */
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enum bfd_reloc_code_real reloc_type;
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int size = imm_size (n);
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int sign;
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if (i.types[n].bitfield.imm32s
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@ -139,6 +139,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "noreg32-data16"
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run_list_test "movx16" "-I${srcdir}/$subdir -al"
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run_list_test "movx32" "-al"
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run_dump_test "sizing32"
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run_dump_test "addr16"
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run_dump_test "addr32"
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run_dump_test "code16"
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@ -1236,5 +1237,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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}
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set ASFLAGS "$old_ASFLAGS --64"
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run_dump_test "sizing64"
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set ASFLAGS "$old_ASFLAGS"
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}
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55
gas/testsuite/gas/i386/sizing.s
Normal file
55
gas/testsuite/gas/i386/sizing.s
Normal file
@ -0,0 +1,55 @@
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.macro insn, mnem:req, opnds:vararg
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.struct
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\mnem \opnds
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.equiv \mnem, .
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.endm
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insn inc %eax
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.equiv .Lis_64bit, inc > 1
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insn add $1, %al
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insn adc $1, %cl
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insn sub $0x12345678, %eax
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insn sbb $0x12345678, %ecx
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insn and $1, %eax
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insn call .
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insn jecxz .
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insn pextrw $0, %xmm0, %eax
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.macro pextrw_store opnds:vararg
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{store} pextrw \opnds
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.endm
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insn pextrw_store $0, %xmm0, %eax
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insn vpextrw $0, %xmm0, %eax
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.macro vpextrw_evex opnds:vararg
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{evex} vpextrw \opnds
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.endm
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insn vpextrw_evex $0, %xmm0, %eax
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.if .Lis_64bit
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insn mov $0x876543210, %rcx
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insn movq 0x876543210, %rax
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.else
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insn lcall $0, $0
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.code16
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insn ljmp $0, $0
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.endif
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insn bextr $0x11223344, %fs:(,%eax,2), %eax
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20
gas/testsuite/gas/i386/sizing32.d
Normal file
20
gas/testsuite/gas/i386/sizing32.d
Normal file
@ -0,0 +1,20 @@
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#name: ix86 insn sizing
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#nm: -B
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#source: sizing.s
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#...
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0+03 a adc
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0+02 a add
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0+03 a and
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0+10 a bextr
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0+05 a call
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0+01 a inc
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0+02 a jecxz
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0+07 a lcall
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0+05 a ljmp
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0+05 a pextrw
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0+06 a pextrw_store
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0+06 a sbb
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0+05 a sub
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0+05 a vpextrw
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0+07 a vpextrw_evex
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20
gas/testsuite/gas/i386/sizing64.d
Normal file
20
gas/testsuite/gas/i386/sizing64.d
Normal file
@ -0,0 +1,20 @@
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#name: x86-64 insn sizing
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#nm: -B
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#source: sizing.s
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#...
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0+03 a adc
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0+02 a add
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0+03 a and
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0+10 a bextr
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0+05 a call
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0+02 a inc
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0+03 a jecxz
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0+0a a mov
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0+0a a movq
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0+05 a pextrw
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0+06 a pextrw_store
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0+06 a sbb
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0+05 a sub
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0+05 a vpextrw
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0+07 a vpextrw_evex
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