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[PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg

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gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant.
	(insns): Change vabs and vneg entries to accept MVE variants.
	* testsuite/gas/arm/mve-vabsneg-bad-1.d: New test.
	* testsuite/gas/arm/mve-vabsneg-bad-1.l: New test.
	* testsuite/gas/arm/mve-vabsneg-bad-1.s: New test.
	* testsuite/gas/arm/mve-vabsneg-bad-2.d: New test.
	* testsuite/gas/arm/mve-vabsneg-bad-2.l: New test.
	* testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
This commit is contained in:
Andre Vieira
2019-05-15 16:52:50 +01:00
parent 5ee9134313
commit 485dee97c6
8 changed files with 161 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
gas/ChangeLog
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@ -1,3 +1,14 @@
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant.
(insns): Change vabs and vneg entries to accept MVE variants.
* testsuite/gas/arm/mve-vabsneg-bad-1.d: New test.
* testsuite/gas/arm/mve-vabsneg-bad-1.l: New test.
* testsuite/gas/arm/mve-vabsneg-bad-1.s: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.d: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.l: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum it_instruction_type): Rename to... * config/tc-arm.c (enum it_instruction_type): Rename to...

13
gas/config/tc-arm.c
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@ -15950,12 +15950,13 @@ do_neon_abs_neg (void)
if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
return; return;
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
return;
rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY); et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
if (check_simd_pred_availability (et.type == NT_float,
NEON_CHECK_ARCH | NEON_CHECK_CC))
return;
inst.instruction |= LOW4 (inst.operands[0].reg) << 12; inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[0].reg) << 22; inst.instruction |= HI1 (inst.operands[0].reg) << 22;
inst.instruction |= LOW4 (inst.operands[1].reg); inst.instruction |= LOW4 (inst.operands[1].reg);
@ -21909,9 +21910,6 @@ static const struct asm_opcode insns[] =
nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
@ -22643,6 +22641,9 @@ static const struct asm_opcode insns[] =
mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
#undef ARM_VARIANT #undef ARM_VARIANT
#define ARM_VARIANT & fpu_neon_ext_v1 #define ARM_VARIANT & fpu_neon_ext_v1
mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),

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gas/testsuite/gas/arm/mve-vabsneg-bad-1.d Normal file
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@ -0,0 +1,6 @@
#name: bad MVE VABS and VNEG instructions
#as: -march=armv8.1-m.main+mve
#error_output: mve-vabsneg-bad-1.l
.*: +file format .*arm.*

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gas/testsuite/gas/arm/mve-vabsneg-bad-1.l Normal file
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@ -0,0 +1,33 @@
[^:]*: Assembler messages:
[^:]*:13: Error: bad type in SIMD instruction -- `vabs.p8 q0,q1'
[^:]*:14: Error: bad type in SIMD instruction -- `vabs.p16 q0,q1'
[^:]*:15: Error: bad type in SIMD instruction -- `vabs.u8 q0,q1'
[^:]*:16: Error: bad type in SIMD instruction -- `vabs.u16 q0,q1'
[^:]*:17: Error: bad type in SIMD instruction -- `vabs.u32 q0,q1'
[^:]*:18: Error: selected FPU does not support instruction -- `vabs.f16 q0,q1'
[^:]*:19: Error: selected FPU does not support instruction -- `vabs.f32 q0,q1'
[^:]*:20: Error: bad type in SIMD instruction -- `vabs.s64 q0,q1'
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Error: bad type in SIMD instruction -- `vneg.p8 q0,q1'
[^:]*:23: Error: bad type in SIMD instruction -- `vneg.p16 q0,q1'
[^:]*:24: Error: bad type in SIMD instruction -- `vneg.u8 q0,q1'
[^:]*:25: Error: bad type in SIMD instruction -- `vneg.u16 q0,q1'
[^:]*:26: Error: bad type in SIMD instruction -- `vneg.u32 q0,q1'
[^:]*:27: Error: selected FPU does not support instruction -- `vneg.f16 q0,q1'
[^:]*:28: Error: selected FPU does not support instruction -- `vneg.f32 q0,q1'
[^:]*:29: Error: bad type in SIMD instruction -- `vneg.s64 q0,q1'
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:32: Error: syntax error -- `vnegeq.s32 q0,q1'
[^:]*:33: Error: syntax error -- `vnegeq.s32 q0,q1'
[^:]*:35: Error: instruction missing MVE vector predication code -- `vneg.s32 q0,q1'
[^:]*:36: Error: vector predicated instruction should be in VPT/VPST block -- `vnegt.s32 q0,q1'

37
gas/testsuite/gas/arm/mve-vabsneg-bad-1.s Normal file
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@ -0,0 +1,37 @@
.macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s32 q0, q1
.endr
.endm
.syntax unified
.text
.thumb
vabs.p8 q0, q1
vabs.p16 q0, q1
vabs.u8 q0, q1
vabs.u16 q0, q1
vabs.u32 q0, q1
vabs.f16 q0, q1
vabs.f32 q0, q1
vabs.s64 q0, q1
cond vabs
vneg.p8 q0, q1
vneg.p16 q0, q1
vneg.u8 q0, q1
vneg.u16 q0, q1
vneg.u32 q0, q1
vneg.f16 q0, q1
vneg.f32 q0, q1
vneg.s64 q0, q1
cond vneg
it eq
vnegeq.s32 q0, q1
vnegeq.s32 q0, q1
vpst
vneg.s32 q0, q1
vnegt.s32 q0, q1

6
gas/testsuite/gas/arm/mve-vabsneg-bad-2.d Normal file
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@ -0,0 +1,6 @@
#name: bad MVE FP VABS and VNEG instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vabsneg-bad-2.l
.*: +file format .*arm.*

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gas/testsuite/gas/arm/mve-vabsneg-bad-2.l Normal file
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@ -0,0 +1,29 @@
[^:]*: Assembler messages:
[^:]*:13: Error: bad type in SIMD instruction -- `vabs.p8 q0,q1'
[^:]*:14: Error: bad type in SIMD instruction -- `vabs.p16 q0,q1'
[^:]*:15: Error: bad type in SIMD instruction -- `vabs.u8 q0,q1'
[^:]*:16: Error: bad type in SIMD instruction -- `vabs.u16 q0,q1'
[^:]*:17: Error: bad type in SIMD instruction -- `vabs.u32 q0,q1'
[^:]*:18: Error: bad type in SIMD instruction -- `vabs.s64 q0,q1'
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:20: Error: bad type in SIMD instruction -- `vneg.p8 q0,q1'
[^:]*:21: Error: bad type in SIMD instruction -- `vneg.p16 q0,q1'
[^:]*:22: Error: bad type in SIMD instruction -- `vneg.u8 q0,q1'
[^:]*:23: Error: bad type in SIMD instruction -- `vneg.u16 q0,q1'
[^:]*:24: Error: bad type in SIMD instruction -- `vneg.u32 q0,q1'
[^:]*:25: Error: bad type in SIMD instruction -- `vneg.s64 q0,q1'
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Error: syntax error -- `vnegeq.f32 q0,q1'
[^:]*:29: Error: syntax error -- `vnegeq.f32 q0,q1'
[^:]*:31: Error: instruction missing MVE vector predication code -- `vneg.f32 q0,q1'
[^:]*:32: Error: vector predicated instruction should be in VPT/VPST block -- `vnegt.f32 q0,q1'

32
gas/testsuite/gas/arm/mve-vabsneg-bad-2.s Normal file
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@ -0,0 +1,32 @@
.macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s32 q0, q1
.endr
.endm
.syntax unified
.text
.thumb
vabs.p8 q0, q1
vabs.p16 q0, q1
vabs.u8 q0, q1
vabs.u16 q0, q1
vabs.u32 q0, q1
vabs.s64 q0, q1
cond vabs
vneg.p8 q0, q1
vneg.p16 q0, q1
vneg.u8 q0, q1
vneg.u16 q0, q1
vneg.u32 q0, q1
vneg.s64 q0, q1
cond vneg
it eq
vnegeq.f32 q0, q1
vnegeq.f32 q0, q1
vpst
vneg.f32 q0, q1
vnegt.f32 q0, q1